CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver
- SCAS859F January 2009 – June 2015 CDCLVP111
  
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DATA SHEET

CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1 Features

Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
Fully Compatible With LVECL and LVPECL
Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typical 15 ps) for Clock-Distribution Applications
- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 350 ps
- Open Input Default State
- LVDS, CML, SSTL Input Compatible
V_BB Reference Voltage Output for Single-Ended Clocking
Available in a 32-Pin LQFP and QFN Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

2 Applications

Designed for Driving 50-Ω Transmission Lines
High Performance Clock Distribution

3 Description

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCLVP111	VQFN (32)	5.00 mm × 5.00 mm
CDCLVP111	LQFP (32)	7.00 mm × 7.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

4 Revision History

Changes from E Revision (July 2011) to F Revision

Added Device Information Table, Pin Configuration and Functions; Specifications; Applications and Implementation; Detailed Description; Layout;Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
Added extended frequency range from 1GHz down to 100MHz Go

Changes from D Revision (March 2010) to E Revision

Changed the PowerPAD Pin Function DescriptionGo

Changes from C Revision (November 2009) to D Revision

Changed the PowerPAD description in the PIN FUNCTIONS table to include the LQFP package information.Go
Deleted duplicate information covering the PowerPAD from Note 1 of the Pin Functions table.Go
Added "NOTE" at the beginning of "Applications and Implementation" section.Go
Changed JEDEC symbol to R_θJAGo

Changes from B Revision (April 2009) to C Revision

Changed PowerPAD information to the Pinout PackageGo
Added PowerPAD information to the Pin Functions tableGo

Changes from A Revision (March 2009) to B Revision

Added LVTTL/LVCMOS functionality compatible.Go
Changed recommended resistor values in Go

Changes from * Revision (January 2009) to A Revision

Changed note referneces within the AC ELECTRICAL CHARACTERISTICS tableGo
Added a Typ value of 0.04ps to the Additive phase jitter in the AC ELECTRICAL CHARACTERISTICS Go

5 Pin Configuration and Functions

RHB, VF, or VFP Package

32-Pin VQFN, LQFP, or HLQFP

Top View

Pin Functions⁽¹⁾

PIN		TYPE	DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
CLK_SEL	2	Input	Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible.
CLK0, CLK0	3	Input	Differential LVECL/LVPECL input pair
CLK0, CLK0	4
CLK1, CLK1	6
CLK1, CLK1	7
Q [9:0]	11	Output	LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn.
	13
	15
	18
	20
	22
	24
	27
	29
	31
Q[9:0]	10	Output	LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn.
	12
	14
	17
	19
	21
	23
	26
	28
	30
V_BB	5	—	Reference voltage output for single-ended input operation
V_CC	1	Power	Supply voltage
	9
	16
	25
	32
V_EE	8	Ground	Device ground or negative supply voltage in ECL mode
PowerPAD™	0	Ground	The PowerPAD of the QFN32 is thermally connected to the die to improve the heat transfer out of the package. The pad of the QFN32 with PowerPAD must be connected to V_EE.

(1) CLKn, CLK_SEL pulldown resistor = 75 kΩ; CLKn pullup resistor = 37.5 kΩ; CLKn pulldown resistor = 50 kΩ.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage (Relative to V_EE)	–0.3	4.6	V
V_I	Input voltage	–0.3	V_CC + 0.5	V
V_O	Output voltage	–0.3	V_CC + 0.5	V
I_IN	Input current		±20	mA
V_EE	Negative supply voltage (Relative to V_CC)	–4.6	0.3	V
I_BB	Sink/source current	–1	1	mA
I_O	DC output current		–50	mA
T_J	Maximum operating junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	3000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage (relative to V_EE)	2.375	2.5/3.3	3.8	V
T_A	Operating free-air temperature	–40		85	°C/W
T_J	Operating junction temperature			110	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		CDCLVP111		UNIT
		RHB (VQFN)	VF (LQFP)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	45.2	85.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	37.5	23.2	°C/W
R_θJB	Junction-to-board thermal resistance	17.9	49.4	°C/W
ψ_JT	Junction-to-top characterization parameter	1.5	0.9	°C/W
ψ_JB	Junction-to-board characterization parameter	17.9	48.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	9.7	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics, LVECL

Vsupply: V_CC = 0 V, V_EE = –2.375 V to –3.8 V over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_EE	Supply internal current	Absolute value of current	–40°C, 25°C, 85°C	40		85	mA
I_CC	Output and internal supply current	All outputs terminated 50 Ω to V_CC – 2 V	–40°C			354	mA
			25°C			380
			85°C			405
I_IN	Input current	Includes pullup/pulldown resistors, V_IH = V_CC, V_IL = V_CC - 2 V	–40°C, 25°C, 85°C	–150		150	μA
V_BB	Internally generated bias voltage	For V_EE= –3 to –3.8 V, I_BB= –0.2 mA	–40°C, 25°C, 85°C	–1.45	–1.3	–1.15	V
V_BB	Internally generated bias voltage	V_EE= –2.375 to –2.75 V, I_BB = –0.2 mA	–40°C, 25°C, 85°C	–1.4	–1.25	–1.1	V
V_IH	High-level input voltage (CLK_SEL)		–40°C, 25°C, 85°C	–1.165		–0.88	V
V_IL	Low-level input voltage (CLK_SEL)		–40°C, 25°C, 85°C	–1.81		–1.475	V
V_ID	Input amplitude (CLKn, CLKn)	Difference of input, see ⁽¹⁾	–40°C, 25°C, 85°C	0.5		1.3	V
V_CM	Common-mode voltage (CLKn, CLKn)	DC offset relative to V_EE	–40°C, 25°C, 85°C	V_EE + 1		–0.3	V
V_OH	High-level output voltage	I_OH = –21 mA	–40°C	–1.26		–0.85	V
			25°C	–1.2		–0.85
			85°C	–1.15		–0.85
V_OL	Low-level output voltage	I_OL = –5 mA	–40°C	–1.85		–1.5	V
			25°C	–1.85		–1.45
			85°C	–1.85		–1.4
V_OD	Differential output voltage swing	Terminated with 50 Ω to V_CC –2 V, see Figure 5	–40°C, 25°C, 85°C	600			mV

(1) V_ID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum V_ID of 100 mV.

6.6 DC Electrical Characteristics, LVPECL

Vsupply: V_CC = 2.375 V to 3.8 V, V_EE= 0 V over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_EE	Supply internal current	Absolute value of current	–40°C, 25°C, 85°C	40		85	mA
I_CC	Output and internal supply current	All outputs terminated 50 Ω to V_CC – 2 V	-40°C			354	mA
			25°C			380
			85°C			405
I_IN	Input current	Includes pullup/pulldown resistors V_IH=V_CC, V_IL= V_CC–2V	–40°C, 25°C, 85°C	–150		150	μA
V_BB	Internally generated bias voltage	V_CC= 3 to 3.8 V, I_BB= –0.2 mA	–40°C, 25°C, 85°C	V_CC – 1.45	V_CC – 1.3	V_CC – 1.15	V
V_BB	Internally generated bias voltage	V_CC= 2.375 to 2.75 V, I_BB = –0.2 mA	–40°C, 25°C, 85°C	V_CC – 1.4	V_CC – 1.25	V_CC – 1.1	V
V_IH	High-level input voltage (CLK_SEL)		–40°C, 25°C, 85°C	V_CC – 1.165		V_CC – 0.88	V
V_IL	Low-level input voltage (CLK_SEL)		–40°C, 25°C, 85°C	V_CC – 1.81		V_CC – 1.475	V
V_ID	Input amplitude (CLKn, CLKn)	Difference of inpu, see ⁽¹⁾,	–40°C, 25°C, 85°C	0.5		1.3	V
V_CM	Common-mode voltage (CLKn, CLKn)	DC offset relative to V_EE	–40°C, 25°C, 85°C	1		V_CC – 0.3	V
V_OH	High-level output voltage	I_OH = –21 mA	–40°C	V_CC – 1.26		V_CC – 0.85	V
			25°C	V_CC – 1.2		V_CC – 0.85
			85°C	V_CC – 1.15		V_CC – 0.85
V_OL	Low-level output voltage	I_OL = –5 mA	–40°C	V_CC – 1.85		V_CC – 1.5	V
			25°C	V_CC – 1.85		V_CC – 1.45
			85°C	V_CC – 1.85		V_CC – 1.4
V_OD	Differential output voltage swing	Terminated with 50 Ω to V_CC - 2 V, see Figure 5	–40°C, 25°C, 85°C	600			mV

6.7 AC Electrical Characteristics

Vsupply: V_CC = 2.375 V to 3.8 V, V_EE = 0 V or LVECL/LVPECL input V_CC = 0 V, V_EE = -2.375 V to -3.8 V over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_pd	Differential propagation delay CLKn, CLKn to all Q0, Q0… Q9, Q9	See Note D in Figure 2	200		350	ps
t_sk(o)	Output-to-output skew	See Note A in Figure 2		15	30	ps
t_sk(pp)	Part-to-part skew	See Note B in Figure 2			70	ps
t_aj	Additive phase jitter	Integration bandwidth of 20 kHz to 20 MHz, fout = 125 MHz at 25°CC		0.04	< 0.8	ps
f_(max)	Maximum frequency	Functional up to 3.5 GHz			3500	MHz
t_r/t_f	Output rise and fall time (20%, 80%)	See Note D in Figure 2	90		200	ps

6.8 Typical Characteristics

Figure 1. LVPECL Input Using CLK0 Pair, V_CM = 1 V, V_ID= 0.5 V

7 Parameter Measurement Information

7.1 Test Configurations

A. Output skew is calculated as the greater of: The difference between the fastest and the slowest t_PLHn (n = 0, 1,...9) or the difference between the fastest and the slowest t_PHLn (n = 0, 1,...9).

B. Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest t_PLHn (n = 0, 1,...9) across multiple devices or the difference between the fastest and the slowest t_PHLn (n = 0, 1,...9) across multiple devices.

C. Typical value measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz.

D. Input conditions: V_CM = 1 V, V_ID = 0.5 V and F_IN = 1 GHz.

Figure 2. Waveform for Calculating Both Output and Part-to-Part Skew

Figure 3. Output Voltage and Rise and Fall Time

Figure 4. Typical Termination for Output Driver (See the Interfacing Between LVPECL, LVDS, and CML Application Note, SCAA056)

CDCLVP111 ai_test_lvpecl_dc_out_cas880.png

Figure 5. LVPECL Output DC Configuration During Device Test

CDCLVP111 ai_test_lvpecl_ac_out_cas880.png

Figure 6. LVPECL Output AC Configuration During Device Test

8 Detailed Description

8.1 Overview

The CDCLVP111 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (V_CC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 8 (a and b) for V_CC = 2.5 V and Figure 9 (a and b) for V_CC = 3.3 V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVP111 is a low-additive jitter universal to LVPECL fan out buffer with 2 selectable inputs. The small package, low-output skew, and low-additive jitter make for a flexible device in demanding applications.

8.4 Device Functional Modes

Select Input Terminal By CLK_SEL Pin

Table 1. Function Table

CLK_SEL	ACTIVE CLOCK INPUT
0	CLK0, CLK0
1	CLK1, CLK1

The two inputs of the CDCLVP111 are internally mixed together and can be selected through the control pin. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the CDCLVP111 to provide greater system flexibility.

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVP111 is a low-additive jitter LVPECL fanout buffer that can generate 5 copies of 2 selectable LVDS, CML or SSTL inputs. The CDCLVP111 can accept reference clock frequencies up to 3.5 GHz while providing low-output skew.

9.2 Typical Application

9.2.1 Fanout Buffer for Line Card Application

Figure 7. CDCLVP111 Block Diagram

9.2.1.1 Design Requirements

The CDCLVP111 shown in Figure 7 is configured to be able to select 2 inputs, a 156.25-MHz LVPECL clock from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line card application with the following properties:

The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP111 will need to be provided with 86-Ω emitter resistors near the driver for proper operation.
The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP111. This ASIC features internal termination so no additional components are needed.
The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are placed near the CDCLVP111 and a 0.1-uF are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.

9.2.1.2 Detailed Design Procedure

Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power-supply filtering and bypassing is critical for low-noise applications.

See Figure 18 for recommended filtering techniques.

9.2.1.2.1 LVPECL Output Termination

Refer to Figure 8 for output termination schemes depending on the receiver application.

CDCLVP111 ai_lvpecl_dc_ac_out_25_scas859.gif

Figure 8. LVPECL Output DC and AC Termination for V_CC = 2.5 V

CDCLVP111 ai_lvpecl_dc_ac_out_33_scas859.gif

Figure 9. LVPECL Output DC and AC Termination for V_CC = 3.3 V

9.2.1.2.2 Input Termination

The CDCLVP111 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 10 illustrates how to DC couple an LVCMOS input to the CDCLVP111. The series resistance (R_S) should be placed close to the LVCMOS driver; the value is calculated as the difference between the transmission line impedance and the driver output impedance.

Refer to Figure 10 for proper input terminations, dependent on single ended or differential inputs.

Figure 10. DC-Coupled LVCMOS Input to CDCLVP111

Figure 11 shows how to DC couple LVDS inputs to the CDCLVP111. Figure 12 and Figure 13 describe the method of DC coupling LVPECL inputs to the CDCLVP111 for V_CC = 2.5 V and V_CC = 3.3 V, respectively.

Figure 11. DC-Coupled LVDS Inputs to CDCLVP111

CDCLVP111 ai_dc_lvpecl_in_25v_scas859.gif

Figure 12. DC-Coupled LVPECL Inputs to CDCLVP111 (V_CC = 2.5 V)

CDCLVP111 ai_dc_lvpecl_in_33v_scas859.gif

Figure 13. DC-Coupled LVPECL Inputs to CDCLVP111 (V_CC = 3.3 V)

Figure 14 and Figure 15 show the technique of AC coupling differential inputs to the CDCLVP111 for V_CC = 2.5 V and V_CC = 3.3 V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.

Figure 14. AC-Coupled Differential Inputs to CDCLVP111 (V_CC = 2.5 V)

Figure 15. AC-Coupled Differential Inputs to CDCLVP111 (V_CC = 3.3 V)

9.2.1.3 Application Curves

The CDCLVP111 low-additive noise can be shown in this line card application. The low-noise, 156.25-MHz signal with 53-fs RMS jitter drives the CDCLVP111, resulting in 86-fs RMS when integrated from 10 kHz to 20 MHz. The resultant-additive jitter is a low 68-fs RMS for this configuration.

Reference signal is low noise signal generator

Figure 16. CDCLVP111 Reference Phase Noise 32 fs rms
(10 kHz to 20 MHz)

Figure 17. CDCLVP111 Output Phase Noise 57 fs rms
(10 kHz to 20 MHz)

10 Power Supply Recommendations

10.1 Power-Supply Filtering

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter and phase noise is very critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low-impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI recommends to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply terminals in the package. TI recommends, but does not require, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low dc resistance to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation.

Figure 18 illustrates this recommended power-supply decoupling method.

Figure 18. Power-Supply Decoupling