SCAS880F August   2009  – September 2015 CDCLVP1204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Terminal Characteristics
    6. 6.6  Electrical Characteristics: LVCMOS Input
    7. 6.7  Electrical Characteristics: Differential Input
    8. 6.8  Electrical Characteristics: LVPECL Output
    9. 6.9  Electrical Characteristics: LVPECL Output
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

7.1 Test Configurations

Figure 5 through Figure 11 illustrate how the device must be set up for a variety of test configurations for each block for the CDCLVP1204.

CDCLVP1204 ai_test_lvpecl_dc_in_cas880.gifFigure 5. DC-Coupled LVPECL Input During Device Test
CDCLVP1204 ai_test_lvcmos_dc_in_cas880.gifFigure 6. DC-Coupled LVCMOS Input During Device Test
CDCLVP1204 ai_vth_var_lvcmos_in_cas880.gifFigure 7. Voltage Variation Over LVCMOS Vth Levels
CDCLVP1204 ai_test_lvds_dc_in_cas880.gifFigure 8. DC-Coupled LVDS Input During Device Test
CDCLVP1204 ai_test_diff_ac_in_cas880.gifFigure 9. AC-Coupled Differential Input To Device
CDCLVP1204 ai_test_lvpecl_dc_out_cas880.gifFigure 10. LVPECL Output DC Configuration During Device Test
CDCLVP1204 ai_test_lvpecl_ac_out_cas880.gifFigure 11. LVPECL Output AC Configuration During Device Test