SCAS886E August   2009  – December 2015 CDCLVP1212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: LVCMOS Input
    6. 7.6  Electrical Characteristics: Differential Input
    7. 7.7  Electrical Characteristics: LVPECL Output, At VCC = 2.375 V to 2.625 V
    8. 7.8  Electrical Characteristics: LVPECL Output, at VCC = 3.0 V to 3.6 V
    9. 7.9  Pin Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVPECL Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Fanout Buffer for Line Card Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The CDCLVP1212 is a low additive jitter LVPECL fanout buffer that can generate four copies of two selectable LVPECL, LVDS, or LVCMOS inputs. The CDCLVP1212 can accept reference clock frequencies up to 2 GHz while providing low output skew.

10.2 Typical Application

10.2.1 Fanout Buffer for Line Card Application

Figure 20. CDCLVP1212 Block Diagram

10.2.1.1 Design Requirements

The CDCLVP1212 shown in Figure 20 is configured to be able to select two inputs, a 156.25-MHz LVPECL clock from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line card application with the following properties:

  • The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP1212 will need to be provided with 86-Ω emitter resistors near the driver for proper operation.
  • The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP1212. This ASIC features internal termination so no additional components are needed.
  • The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are placed near the CDCLVP1212 and 0.1-uF capacitors are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.

10.2.1.2 Detailed Design Procedure

Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.

Refer to LVPECL Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is critical for low noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on the CDCLVP1212 Evaluation Module at SCAU036.

10.2.1.3 Application Curves

CDCLVP1212 ref_noise_1204.png
1. Reference signal is low noise Crystek XO CPRO33.156.25
Figure 21. CDCLVP12xx Reference Phase Noise 32 fs rms
(10 kHz to 20 MHz)
CDCLVP1212 output_noise_1204.png
 
Figure 22. CDCLVP12xx Output Phase Noise 57 fs rms
(10 kHz to 20 MHz)

The low additive noise of the CDCLVP12xx can be shown in this line card application. The low noise 156.25-MHz XO with 32-fs RMS jitter drives the CDCLVP12xx, resulting in 57-fs RMS when integrated from 10 kHz to 20 MHz. The resultant additive jitter is a low 47-fs RMS for this configuration.