JAJSED0G May   2012  – January 2018 CDCM6208

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information, Airflow = 0 LFM
    5. 6.5  Thermal Information, Airflow = 150 LFM
    6. 6.6  Thermal Information, Airflow = 250 LFM
    7. 6.7  Thermal Information, Airflow = 500 LFM
    8. 6.8  Single-Ended Input Characteristics (SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL)
    9. 6.9  Single-Ended Input Characteristics (PRI_REF, SEC_REF)
    10. 6.10 Differential Input Characteristics (PRI_REF, SEC_REF)
    11. 6.11 Crystal Input Characteristics (SEC_REF)
    12. 6.12 Single-Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
    13. 6.13 PLL Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 LVPECL (High-Swing CML) Output Characteristics
    16. 6.16 CML Output Characteristics
    17. 6.17 LVDS (Low-Power CML) Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Output Skew and Sync to Output Propagation Delay Characteristics
    20. 6.20 Device Individual Block Current Consumption
    21. 6.21 Worst Case Current Consumption
    22. 6.22 Timing Requirements, I2C Timing
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Typical Device Jitter
      2. 8.3.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.3.3  VCO Calibration
      4. 8.3.4  Reference Divider (R)
      5. 8.3.5  Input Divider (M)
      6. 8.3.6  Feedback Divider (N)
      7. 8.3.7  Prescaler Dividers (PS_A, PS_B)
      8. 8.3.8  Phase Frequency Detector (PFD)
      9. 8.3.9  Charge Pump (CP)
      10. 8.3.10 Fractional Output Divider Jitter Performance
      11. 8.3.11 Device Block-Level Description
      12. 8.3.12 Device Configuration Control
      13. 8.3.13 Configuring the RESETN Pin
      14. 8.3.14 Preventing False Output Frequencies in SPI/I2C Mode at Start-Up
      15. 8.3.15 Input MUX and Smart Input MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pins Definition
      2. 8.4.2 Loop Filter Recommendations for Pin Modes
      3. 8.4.3 Status Pins Definition
      4. 8.4.4 PLL Lock Detect
      5. 8.4.5 Interface and Control
        1. 8.4.5.1 Register File Reference Convention
        2. 8.4.5.2 SPI - Serial Peripheral Interface
          1. 8.4.5.2.1 Writing to the CDCM6208
          2. 8.4.5.2.2 Reading From the CDCM6208
          3. 8.4.5.2.3 Block Write/Read Operation
          4. 8.4.5.2.4 I2C Serial Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Jitter Considerations in SERDES Systems
        2. 9.2.2.2  Jitter Considerations in ADC and DAC Systems
        3. 9.2.2.3  Configuring the PLL
        4. 9.2.2.4  Programmable Loop Filter
        5. 9.2.2.5  Loop filter Component Selection
        6. 9.2.2.6  Device Output Signaling
        7. 9.2.2.7  Integer Output Divider (IO)
        8. 9.2.2.8  Fractional Output Divider (FOD)
        9. 9.2.2.9  Output Synchronization
        10. 9.2.2.10 Output Mux on Y4 and Y5
        11. 9.2.2.11 Staggered CLK Output Power Up for Power Sequencing of a DSP
  10. 10Power Supply Recommendations
    1. 10.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 10.1.1 Mixing Supplies
      2. 10.1.2 Power-On Reset
      3. 10.1.3 Slow Power-Up Supply Ramp
      4. 10.1.4 Fast Power-Up Supply Ramp
      5. 10.1.5 Delaying VDD_Yx_Yy to Protect DSP IOs
    2. 10.2 Device Power-Up Timing
    3. 10.3 Power Down
    4. 10.4 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Reference Schematics
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Register Maps

In SPI/I2C mode the device can be configured through twenty registers. Register 4 configures the input, Reg 0-3 the PLL and dividers, and Register 5 - 20 configures the 8 different outputs.

CDCM6208 Device_Register_Map_SCAS931.gifFigure 47. Device Register Map

Table 17. Register 0

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:10 RESERVED These bits must be set to 0
9:7 LF_C3[2:0] PLL Internal Loop Filter (C3) PLL Internal Loop Filter Capacitor (C3) Selection
000 → 35 pF
001→ 112.5 pF
010 → 177.5 pF
011 → 242.5 pF
100 → 310 pF
101 → 377.5 pF
110 → 445 pF
111 → 562.5 pF
6:4 LF_R3[2:0] PLL Internal Loop Filter (R3) PLL Internal Loop Filter Resistor (R3) Selection
000 → 10 Ω
001 → 30 Ω
010 → 60 Ω
011 → 100 Ω
100 → 530 Ω
101→ 1050 Ω
110 → 2080 Ω
111 → 4010 Ω
3:1 PLL_ICP[2:0] PLL Charge Pump PLL Charge Pump Current Setting
000 → 500 µA
001 → 1.0 mA
010 → 1.5 mA
011 → 2.0 mA
100 → 2.5 mA
101 → 3.0 mA
110 → 3.5 mA
111→ 4.0 mA
0 RESERVED This bit is tied to one statically, and it is recommended to set to 1 when writing to register.

Table 18. Register 1

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:2 PLL_REFDIV[13:0] PLL Reference Divider PLL Reference 14-b Divider Selection
(Divider value is register value +1)
1:0 PLL_FBDIV1[9:8] PLL Feedback Divider 1 PLL Feedback 10-b Divider Selection, Bits 9:8

Table 19. Register 2

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:8 PLL_FBDIV1[7:0] PLL Feedback Divider 1 PLL Feedback 10-b Divider Selection, Bits 7:0
(Divider value is register value +1)
7:0 PLL_FBDIV0[7:0] PLL Feedback Divider 0 PLL Feedback 8-b Divider Selection
(Divider value is register value +1)

Table 20. Register 3

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:13 RESERVED These bits must be set to 0
12 ST1_SEL_REFCLK Device Status Reference clock status enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
11 ST1_LOR_EN Loss-of-reference Enable on Status 1 pin:
0 → Disable"
1 → Enable (See Table 12 for full description)
10 ST1_PLLLOCK_EN PLL Lock Indication Enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
9 ST0_SEL_REFCLK Reference clock status enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
8 ST0_LOR_EN Loss-of-reference Enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 12 for full description)
7 ST0_PLLLOCK_EN PLL Lock Indication Enable on Status 0 pin:"
0 → Disable
1 → Enable (See Table 12 for full description)
6 RSTN Device Reset Device Reset Selection:
0 → Device In Reset (retains register values)
1 → Normal Operation
5 SYNCN Output Divider Output Channel Dividers Synchronization Enable:
0 → Forces synchronization
1 → Exits synchronization
4 ENCAL PLL/VCO PLL/VCO Calibration Enable:
0 → Disable
1 → Enable
3:2 PS_B[1:0] PLL Prescaler Divider B PLL Prescaler 1 Integer Divider Selection:
00 → Divide-by-4
01→ Divide-by-5
10 → Divide-by-6
11 → RESERVED
used for Y2, Y3, Y6, and Y7
1:0 PS_A[1:0] PLL Prescaler Divider A PLL Prescaler 0 Integer Divider Selection:
00 → Divide-by-4
01 → Divide-by-5
10 → Divide-by-6
11 → RESERVED
used in PLL feedback, Y0, Y1, Y4, and Y5

Table 21. Register 4

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:14 SMUX_PW[1:0] Reference Input Smart MUX Smart MUX Pulse Width Selection. This bit controls the Smart MUX delay and waveform reshaping.
00 → PLL Smart MUX Clock Delay and Reshape Disabled (default in all pin modes)
01 → PLL Smart MUX Clock Delay Enable
10 → PLL Smart MUX Clock Reshape Enable
11 → PLL Smart MUX Clock Delay and Reshape Enable
13 SMUX_MODE_SEL Smart MUX Mode Selection:
0 → Auto select
1 → Manual select
Note: in Auto select mode, both input buffers must be enabled. Set R4.5 = 1 and R4.2 = 1
12 SMUX_REF_SEL Smart MUX Selection for PLL Reference:
0 → Primary
1 → Secondary (only if REF_SEL pin is high)
This bit is ignored when smartmux is set to auto select (for example, R4.13 = 0). See Table 12 for details.
11:8 CLK_PRI_DIV[3:0] Primary Input Divider Primary Input (R) Divider Selection:
0000 → Divide by 1
1111 → Divide by 16
7:6 SEC_SELBUF[1:0] Secondary Input Secondary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → Crystal
5 EN_SEC_CLK Secondary input enable:
0 → Disable
1 → Enable
4:3 PRI_SELBUF[1:0] Primary Input Primary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → LVCMOS
2 EN_PRI_CLK Primary input enable:
0 → Disable
1 → Enable
1 SEC_SUPPLY (1) Secondary Input Supply voltage for secondary input:
0 → 1.8 V
1 → 2.5/3.3 V
0 PRI_SUPPLY (2) Primary Input Supply voltage for primary input:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers should be updated after power-up to reflect the true VDD_SEC supply voltage used.
(2) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers should be updated after power-up to reflect the true VDD_PRI supply voltage used.

Table 22. Register 5

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11 RESERVED This bit must be set to 0
10 RESERVED This bit must be set to 0
9 RESERVED This bit must be set to 0
8:7 SEL_DRVR_CH1[1:0] Output Channel 1 Output Channel 1 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
6:5 EN _CH1[1:0] Output channel 1 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
4:3 SEL_DRVR_CH0[1:0] Output Channel 0 Output Channel 0 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
2:1 EN_CH0[1:0] Output channel 0 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
0 SUPPLY_CH0_1 (1) Output Channels 0
and 1		 Output Channels 0 and 1 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 23. Register 6

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11 RESERVED This bit must be set to 0
10 RESERVED This bit must be set to 0
9 RESERVED This bit must be set to 0
8 RESERVED This bit must be set to 0
7:0 OUTDIV0_1[7:0] Output Channels 0
and 1		 Output channels 0 and 1 8-b output integer divider setting
(Divider value is register value +1)

Table 24. Register 7

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11 RESERVED This bit must be set to 0
10 RESERVED This bit must be set to 0
9 RESERVED This bit must be set to 0
8:7 SEL_DRVR_CH3[1:0] Output Channel 3 Output Channel 3 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
6:5 EN_CH3[1:0] Output channel 3 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
4:3 SEL_DRVR_CH2[1:0] Output Channel 2 Output Channel 2 Type Selection:
00, 01 → LVDS
10 → CML"
11 → PECL
2:1 EN_CH2[1:0] Output channel 2 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
0 SUPPLY_CH2_3 (1) Output Channels 2
and 3		 Output Channels 2 and 3 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 25. Register 8

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11 RESERVED This bit must be set to 0
10 RESERVED This bit must be set to 0
9 RESERVED This bit must be set to 0
8 RESERVED This bit must be set to 0
7:0 OUTDIV2_3[7:0] Output Channels 2
and 3		 Output channels 2 and 3 8-b output integer divider setting
(Divider value is register value +1)

Table 26. Register 9

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14:13 OUTMUX_CH4[1:0] Output Channel 4 Output MUX setting for output channel 4:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10 PRE_DIV_CH4[2:0] Output channel 4 fractional divider's 3-b pre-divider setting (this pre-divider is bypassed if Q9.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1 (only for CDCM6208 with fVCO ≤ 2.4 GHz)
All other combinations reserved
9 EN_FRACDIV_CH4 Output channel 4 fractional divider enable:
0 → Disable
1 → Enable
8 LVCMOS_SLEW_CH4 Output channel 4 LVCMOS output slew:
0 → Normal
1 → Slow
7 EN_LVCMOS_N_CH4 Output channel 4 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is enabled)
6 EN_LVCMOS_P_CH4 Output channel 4 positive-side LVCMOS enable:
0 → Disable
1 → Enable
5 RESERVED This bit must be set to 0
4:3 SEL_DRVR_CH4[2:0] Output channel 4 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
2:1 EN_CH4[1:0] Output channel 4 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
0 SUPPLY_CH4 (1) Output channel 4 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 27. Register 10

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11:4 OUTDIV4[7:0] Output Channel 4 Output channel 4 8-b integer divider setting
(Divider value is register value +1)
3:0 FRACDIV4[19:16] Output channel 4 20-b fractional divider setting, bits 19 - 16

Table 28. Register 11

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:0 FRACDIV4[15:0] Output Channel 4 Output channel 4 20-b fractional divider setting, bits 15 - 0

Table 29. Register 12

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14:13 OUTMUX_CH5[1:0] Output Channel 5 Output MUX setting for output channel 5:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10 PRE_DIV_CH5[2:0] Output channel 5 fractional divider's 3-b pre-divider setting (this pre-divider is bypassed if Q12.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208 with fVCO ≤ 2.4GHz)
All other combinations reserved
9 EN_FRACDIV_CH5 Output channel 5 fractional divider enable:
0 → Disable
1 → Enable
8 LVCMOS_SLEW_CH5 Output channel 5 LVCMOS output slew:
0 → Normal
1 → Slow
7 EN_LVCMOS_N_CH5 Output channel 5 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is enabled)
6 EN_LVCMOS_P_CH5 Output channel 5 positive-side LVCMOS enable:
0 → Disable
1 → Enable
5 RESERVED This bit must be set to 0
4:3 SEL_DRVR_CH5[2:0] Output channel 5 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
2:1 EN_CH5[1:0] Output channel 5 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
0 SUPPLY_CH5 (1) Output channel 5Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 30. Register 13

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11:4 OUTDIV5[7:0] Output Channel 5 Output channel 5 8-b integer divider setting
(Divider value is register value +1)
3:0 FRACDIV5[19:16] Output channel 5 20-b fractional divider setting, bits 19-16

Table 31. Register 14

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:0 FRACDIV5[15:0] Output Channel 5 Output channel 5 20-b fractional divider setting, bits 15-0

Table 32. Register 15

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12:10 PRE_DIV_CH6[2:0] Output Channel 6 Output channel 6 fractional divider's 3-b pre-divider setting (this pre-divider is bypassed if Q15.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208V1 with fVCO ≤ 2.4GHz)
All other combinations reserved
9 EN_FRACDIV_CH6 Output channel 6 fractional divider enable:
0 → Disable
1 → Enable
8 LVCMOS_SLEW_CH6 Output channel 6 LVCMOS output slew:
0 → Normal
1 → Slow
7 EN_LVCMOS_N_CH6 Output channel 6 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is enabled)
6 EN_LVCMOS_P_CH6 Output channel 6 positive-side LVCMOS enable:
0 → Disable
1 → Enable
5 RESERVED This bit must be set to 0
4:3 SEL_DRVR_CH6[1:0] Output channel 6 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
2:1 EN_CH6[1:0] Output channel 6 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
0 SUPPLY_CH6 (1) Output channel 6 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 33. Register 16

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11:4 OUTDIV6[7:0] Output Channel 6 Output channel 6 8-b integer divider setting
(Divider value is register value +1)
3:0 FRACDIV6[19:16] Output channel 6 20-b fractional divider setting, bits 19-16

Table 34. Register 17

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:0 FRACDIV6[15:0] Output Channel 6 Output channel 6 20-b fractional divider setting, bits 15-0

Table 35. Register 18

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12:10 PRE_DIV_CH7[2:0] Output Channel 7 Output channel 7 fractional divider's 3-b pre-divider setting (this pre-divider is bypassed if Q18.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1; (only for CDCM6208 with f VCO ≤ 2.4 GHz)
All other combinations reserved
9 EN_FRACDIV_CH7 Output channel 7 fractional divider enable: 0 → Disable, 1 → Enable
8 LVCMOS_SLEW_CH7 Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow
7 EN_LVCMOS_N_CH7 Output channel 7 negative-side LVCMOS enable: 0 → Disable, 1 → Enable (Negative side can only be enabled if positive side is enabled)
6 EN_LVCMOS_P_CH7 Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 → Enable
5 RESERVED This bit must be set to 0
4:3 SEL_DRVR_CH7[2:0] Output channel 7 type selection:00 or 01 → LVDS, 10 → LVCMOS, 11 → HCSL
2:1 EN_CH7[1:0] Output channel 7 enable: 00 → Disable, 01 → Enable, 10 → Drive static low, 11 → Drive static high
0 SUPPLY_CH7 (1) Output channel 7 Supply Voltage Selection: 0 → 1.8 V, 1 → 2.5/3.3 V
(1) It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 36. Register 19

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit must be set to 0
14 RESERVED This bit must be set to 0
13 RESERVED This bit must be set to 0
12 RESERVED This bit must be set to 0
11:4 OUTDIV7[7:0] Output Channel 7 Output channel 7 8-b integer divider setting
(Divider value is register value +1)
3:0 FRACDIV7[19:16] Output channel 7 20-b fractional divider setting, bits 19-16

Table 37. Register 20

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15:0 FRACDIV7[15:0] Output Channel 7 Output channel 7 20-b fractional divider setting, bits 15-0

Table 38. Register 21 (Read Only)

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED This bit will read a 0
14 RESERVED This bit will read a 0
13 RESERVED This bit will read a 0
12 RESERVED This bit will read a 0
11 RESERVED This bit will read a 0
10 RESERVED This bit will read a 0
9 RESERVED This bit will read a 0
8 RESERVED This bit will read a 0
7 RESERVED This bit will read a 0
6 RESERVED This bit will read a 0
5 RESERVED This bit will read a 0
4 RESERVED This bit will read a 0
3 RESERVED This bit will read a 0
2 PLL_UNLOCK Device Status Monitoring Indicates unlock status for PLL (digital):
0 → PLL locked
1 → PLL unlocked
Note: the external output signal on Status 0 or Status 1 uses a reversed logic, and indicates "lock" with a VOH signal and unlock with a VOL signaling level.
1 LOS_REF Loss of reference input observed at input Smart MUX output in observation window for PLL:
0 → Reference input present
1 → Loss of reference input
0 SEL_REF Indicates Reference Selected for PLL:
0 → Primary
1 → Secondary

Table 39. Register 40 (Read Only)

BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION
15 RESERVED Ignore
14 RESERVED Ignore
13 RESERVED Ignore
12 RESERVED Ignore
11 RESERVED Ignore
10 RESERVED Ignore
9 RESERVED Ignore
8 RESERVED Ignore
7 RESERVED Ignore
6 RESERVED Ignore
5:3 VCO_VERSION Device Information Indicates the device version (Read only):
000 → CDCM6208V1
001 → CDCM6208V2
2:0 DIE_REVISION Indicates the silicon die revision (Read only):
00X --> Engineering Prototypes
010 --> Production Material

Table 40. Default Register Setting for SPI/I2C Modes

Register CDCM6208V1 CDCM6208V2
0 0x01B9 0x01B9
1 0x0000 0x0000
2 0x0018 0x0013
3 0x08F4 0x08F5
4 0x30EC 0x30EC
5 0x0132 0x0022
6 0x0003 0x0003
7 0x0022 0x0022
8 0x0003 0x0004
9 0x0202 0x0002
10 0x003B 0x0090
11 0x01EC 0x0000
12 0x0202 0x0002
13 0x003B 0x0090
14 0x01EC 0x0000
15 0x0002 0x0002
16 0x0040 0x0090
17 0x0000 0x0000
18 0x0002 0x0002
19 0x0040 0x0130
20 0x0000 0x0000
: : :
40 0xXX01 0xXX09