JAJSED0G May 2012 – January 2018 CDCM6208
PRODUCTION DATA.
A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity. The following test results were achieved connecting the CDCM6208 to ADC and DACs:
Observation: Up to an IF = 100 MHz, the ADC performance when driven by the CDCM6208 (Figure 53) is similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering (Figure 52).
Conclusion: Therefore, the CDCM6208 is usable for applications up to 100 MHz IF. For IF above 100 MHz, the SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and other outputs running at different integer frequencies.
NOTE
For crosstalk, TI highly recommends configuring both pre-dividers identically, otherwise the SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.
Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208 compared to driving the DAC with a perfect lab source. Therefore, the CDCM6208 provides sufficient low noise to drive a 245.76 MHz DAC.