JAJSH89D May 2012 – April 2019 CDCUN1208LP
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
3.3-V MODE | ||||||
fout | Output frequency range | 0.0008 | 250 | MHz | ||
VOH | LVCMOS high-level output voltage | VDDOx = 2.97 V, IOH = –0.1 mA (All ERC Settings) | 2.9 | V | ||
VDDOx = 2.97 V, IOH = –5 mA (ERC = SLOW) | 2.4 | V | ||||
VDDOx = 2.97 V, IOH = –8 mA (ERC = MED, FAST) | ||||||
VDDOx = 2.97 V, IOH = –6 mA (ERC = SLOW) | 2.2 | V | ||||
VDDOx = 2.97 V, IOH = –10 mA (ERC = MED) | ||||||
VDDOx = 2.97 V, IOH = –12 mA (ERC = FAST) | ||||||
VOL | LVCMOS low-level output voltage | VDDOx = 2.97 V, IOL = 0.1 mA (All ERC Settings) | 0.1 | V | ||
VDDOx = 2.97 V, IOL = 5 mA (ERC = SLOW) | 0.5 | V | ||||
VDDOx = 2.97 V, IOL = 8 mA (ERC = MED, FAST) | ||||||
VDDOx = 2.97 V, IOL = 6 mA (ERC = SLOW) | 0.8 | V | ||||
VDDOx = 2.97 V, IOL = 10 mA (ERC = MED) | ||||||
VDDOx = 2.97 V, IOL = 12 mA (ERC = FAST) | ||||||
IOH | LVCMOS high-level output current | VDDOx = 3.3 V, VO = 0.5 V; TA = 25°C | –73 | mA | ||
VDDOx = 3.3 V, VO = 1.0 V; TA = 25°C | –64 | |||||
VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C | –49 | |||||
IOL | LVCMOS low-level output current | VDDOx = 3.3 V, VO = 2.8 V; TA = 25°C | 78 | mA | ||
VDDOx = 3.3 V, VO = 2.3 V; TA = 25°C | 72 | |||||
VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C | 58 | |||||
tPLH, tPHL | Propagation delay | 5 | ns | |||
tSLEW-RATE | Output rise/fall slew rate | ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF | 1.2 | V/ns | ||
ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF | 3 | |||||
ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF | 6 | |||||
tjitt-add | Additive jitter | fOUT = 100 MHz, 10k-20M integration bandwidth | 280 | fs | ||
tsk(o) | Output skew(2) | 90 | ps | |||
odc | Output duty cycle(1),(3) | fOUT = 100 MHz; Pdiv = 1 | 45% | 55% | ||
tOE | Output enable to stable clock output | Pin mode. fout = 100 MHz, device in active mode with outputs disabled, OE asserted | 2 | µs | ||
tPD | PD de-asserted to stable clock output | Host mode, fout = 100 MHz, device in power down mode, PD de-asserted | 10 | µs | ||
tPU | Time from power applied to stable clock output(4) | Pin mode, fout = 100 MHz, OE asserted, measured from time VDD is valid to stable output. | 1 | ms |