12.1 Layout Guidelines
TI recommends the following layout guidelines for designing in the CDCVF2505 on a printed-circuit board:
- Provide a full ground or reference plane for the clock traces and the decoupling section.
- Ground floods including stitching using VIAs help prevent the clock injecting spectral lines to surrounding components.
- The decoupling must be placed very close to the device package. The decoupling capacitors can also be placed on the bottom layer of the board. See Design and Layout Guidelines for the CDCVF2505 Clock Driver (SCAA045) for detailed recommendations.
- The CLKOUT pin can have a very short connection to tuning capacitors for the internal feedback.