JAJSMO9B October 2001 – January 2022 CDCVF25081
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The CDCVF25081 operates from a 3.3-V supply. Table 8-2 shows the output logic states of the device based on the selection pins. Based on the input selection pins (S1 and S2), the two output banks can be set as PLL outputs, bypassed PLL outputs, or high impedance.
| S2 | S1 | Bank 1 | Bank 2 | OUTPUT SOURCE | PLL SHUTDOWN |
|---|---|---|---|---|---|
| 0 | 0 | Hi-Z | Hi-Z | N/A | Yes |
| 0 | 1 | Active | Hi-Z | PLL(1) | No |
| 1 | 0 | Active | Active | Input clock (PLL bypass) | Yes |
| 1 | 1 | Active | Active | PLL(1) | No |