JAJST12E April   2004  – February 2024 CDCVF2509

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Dissipation Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Package Thermal Resistance
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  7. 5Parameter Measurement Information
  8. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 サポート・リソース
    3. 6.3 Trademarks
    4. 6.4 静電気放電に関する注意事項
    5. 6.5 用語集
  9. 7Revision History
  10. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|24
サーマルパッド・メカニカル・データ
発注情報

Pin Configuration and Functions

GUID-E262D16C-277D-4BF2-8910-2866AA3544E8-low.gif
Table 4-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
CLK24IClock input. CLK provides the clock signal to be distributed by the CDCVF2509A clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal.
FBIN13IFeedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
1G11IOutput bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK.
2G14IOutput bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK.
FBOUT12OFeedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor.
1Y (0:4)3, 4, 5, 8, 9OClock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output has an integrated 25-Ω series-damping resistor.
2Y (0:3)16, 17, 21, 20OClock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output has an integrated 25-Ω series-damping resistor.
AVCC23PowerAnalog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
AGND1GroundAnalog ground. AGND provides the ground reference for the analog circuitry.
VCC2, 10, 15, 22PowerPower supply
GND6, 7, 18, 19GroundGround