over recommended ranges of supply voltage and operating free-air temperature | MIN | MAX | UNIT |
|---|
| fclk | Clock frequency | 50 | 175 | MHz |
| Input clock duty cycle | 40% | 60% | |
| Stabilization time(1) | | 1 | ms |
(1) The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.