CSD17507Q5A 30-V N-Channel NexFET™ Power MOSFET
- SLPS243G July 2010 – January 2017 CSD17507Q5A
  
  PRODUCTION DATA.

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DATA SHEET

CSD17507Q5A 30-V N-Channel NexFET™ Power MOSFET

1 Features

Ultra-Low Q_g and Q_gd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package

2 Applications

Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems
Optimized for Control FET Applications

3 Description

This 30-V, 9-mΩ, SON 5-mm × 6-mm NexFET™ power MOSFET has been designed to minimize losses in power conversion applications.

Top View

Product Summary

T_A = 25°C		TYPICAL VALUE		UNIT
V_DS	Drain-to-Source Voltage	30		V
Q_g	Gate Charge Total (4.5 V)	2.8		nC
Q_gd	Gate Charge Gate-to-Drain	0.7		nC
R_DS(on)	Drain-to-Source On Resistance	V_GS= 4.5 V	11.8	mΩ
R_DS(on)	Drain-to-Source On Resistance	V_GS = 10 V	9	mΩ
V_GS(th)	Threshold Voltage	1.6		V

Device Information⁽¹⁾

DEVICE	MEDIA	QTY	PACKAGE	SHIP
CSD17507Q5A	13-Inch Reel	2500	SON 5.00-mm × 6.00-mm Plastic Package	Tape and Reel
CSD17507Q5AT	7-Inch Reel	250	SON 5.00-mm × 6.00-mm Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C (unless otherwise stated)		VALUE	UNIT
V_DS	Drain-to-Source Voltage	30	V
V_GS	Gate-to-Source Voltage	±20	V
I_D	Continuous Drain Current	65	A
	Continuous Drain Current (Silicon Limited), T_C = 25°C	61
	Continuous Drain Current⁽¹⁾	14
I_DM	Pulsed Drain Current, T_C = 25°C⁽²⁾	163	A
P_D	Power Dissipation⁽¹⁾	3.1	W
P_D	Power Dissipation, T_C = 25°C	39	W
T_J, T_STG	Operating Junction, Storage Temperature	–55 to 150	°C
E_AS	Avalanche Energy, Single Pulse I_D = 30 A, L = 0.1 mH, R_G = 25 Ω	45	mJ

Typical R_θJA = 40°C/W on a 1-in², 2-oz Cu pad on a
0.06-in thick FR4 PCB.
Max R_θJC = 2°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%.

R_DS(on) vs V_GS

Gate Charge

4 Revision History

Changes from F Revision (November 2016) to G Revision

Corrected package size in the Description sectionGo

Changes from E Revision (July 2011) to F Revision

Changed Description text. Go
Added silicon limited continuous drain current to Absolute Maximum Ratings table. Go
Changed Note 2 in Absolute Maximum Ratings table. Go
Changed THERMAL CHARACTERISTICS table to Thermal Information table. Go
Changed R_θJC from 1.9°C/W : to 2.1°C/W. Go
Changed R_θJA from 51°C/W : to 50°C/W. Go
Added Device and Documentation Support section. Go
Changed MECHANICAL DATA section to Mechanical, Packaging, and Orderable Information section. Go

Changes from D Revision (December 2010) to E Revision

Changed V_GS in the Abs Max Ratings table From: +20/-12 V To: ±20 V. Go
Changed I_GSS Test Conditions from V_GS = 20 V +20/-12 V : to V_GS = 20 V. Go

Changes from C Revision (November 2010) to D Revision

Changed g_fs Transconductance TYP value From: 16 S To: 44 S. Go

Changes from B Revision (September 2010) to C Revision

Added Stencil Recommendation illustration. Go

Changes from A Revision (August 2010) to B Revision

Absolute Maximum Ratings, changed the E_AS value from 145 to 45 mJ. Go

Changes from * Revision (July 2010) to A Revision

Changed the Y axis scale for Figure 5. Go

5 Specifications

5.1 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage	V_GS = 0 V, I_DS = 250 μA	30			V
I_DSS	Drain-to-source leakage current	V_GS = 0 V, V_DS = 24 V			1	μA
I_GSS	Gate-to-source leakage current	V_DS = 0 V, V_GS = 20 V			100	nA
V_GS(th)	Gate-to-source threshold voltage	V_DS = V_GS, I_DS = 250 μA	1.1	1.6	2.1	V
R_DS(on)	Drain-to-source on resistance	V_GS = 4.5 V, I_DS = 11 A		11.8	16.1	mΩ
R_DS(on)	Drain-to-source on resistance	V_GS = 10 V, I_DS = 11 A		9.0	10.8	mΩ
g_fs	Transconductance	V_DS = 15 V, I_DS = 11 A		44		S
DYNAMIC CHARACTERISTICS
C_iss	Input capacitance	V_GS = 0 V, V_DS = 15 V, ƒ = 1 MHz		410	530	pF
C_oss	Output capacitance			270	350	pF
C_rss	Reverse transfer capacitance			23	30	pF
R_G	Series gate resistance			0.7	1.4	Ω
Q_g	Gate charge total (4.5 V)	V_DS = 15 V, I_DS = 11 A		2.8	3.6	nC
Q_gd	Gate charge gate-to-drain			0.7		nC
Q_gs	Gate charge gate-to-source			1.3		nC
Q_g(th)	Gate charge at Vth			0.7		nC
Q_oss	Output charge	V_DS = 13 V, V_GS = 0 V		7.2		nC
t_d(on)	Turnon delay time	V_DS = 15 V, V_GS = 4.5 V, I_DS = 11 A, R_G = 2 Ω		4.7		ns
t_r	Rise time			5.2		ns
t_d(off)	Turnoff delay time			5.7		ns
t_f	Fall time			2.3		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage	I_SD = 11 A, V_GS = 0 V		0.85	1	V
Q_rr	Reverse recovery charge	V_DS= 13 V, I_F = 11 A, di/dt = 300 A/μs		11		nC
t_rr	Reverse recovery time	V_DS= 13 V, I_F = 11 A, di/dt = 300 A/μs		16		ns

5.2 Thermal Information

T_A = 25°C (unless otherwise stated)

PARAMETER		MIN	TYP	MAX	UNIT
R_θJC	Thermal resistance junction-to-case⁽¹⁾			2.1	°C/W
R_θJA	Thermal resistance junction-to-ambient⁽¹⁾⁽²⁾			50	°C/W

(1) R_θJC is determined with the device mounted on a 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. R_θJC is specified by design, whereas R_θJA is determined by the user’s board design.

(2) Device mounted on FR4 material with 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu.

Max R_θJA = 50°C/W when mounted on 1 in² (6.45 cm²) of 2-oz (0.071-mm) thick Cu.

Max R_θJA = 125°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

T_A = 25°C (unless otherwise stated)

Figure 1. Transient Thermal Impedance

Figure 2. Saturation Characteristics

I_D = 11 A

V_DS = 15 V

Figure 4. Gate Charge

I_D = 250 µA

Figure 6. Threshold Voltage vs Temperature

I_D = 11 A, V_GS = 10 V

Figure 8. Normalized On-State Resistance vs Temperature

Single pulse, max R_θJC = 2.1°C/W

Figure 10. Maximum Safe Operating Area

Figure 12. Maximum Drain Current vs Temperature

V_DS = 5 V

Figure 3. Transfer Characteristics

Figure 5. Capacitance

I_D = 11 A

Figure 7. On-State Resistance vs Gate-to-Source Voltage

Figure 9. Typical Diode Forward Voltage

Figure 11. Single Pulse Unclamped Inductive Switching

6 Device and Documentation Support

6.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

6.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

6.3 Trademarks

NexFET, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

6.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

6.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

7 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

7.1 Q5A Package Dimensions

DIM	MILLIMETERS
DIM	MIN	NOM	MAX
A	0.90	1.00	1.10
b	0.33	0.41	0.51
c	0.20	0.25	0.34
D1	4.80	4.90	5.00
D2	3.61	3.81	4.02
E	5.90	6.00	6.10
E1	5.70	5.75	5.80
E2	3.38	3.58	3.78
E3	3.03	3.13	3.23
e	1.17	1.27	1.37
e1	0.27	0.37	0.47
e2	0.15	0.25	0.35
H	0.41	0.56	0.71
K	1.10	—	—
L	0.51	0.61	0.71
L1	0.06	0.13	0.20
θ	0°	—	12°

7.2 Recommended PCB Pattern

DIM	MILLIMETERS		INCHES
DIM	MIN	MAX	MIN	MAX
F1	6.205	6.305	0.244	0.248
F2	4.46	4.56	0.176	0.18
F3	4.46	4.56	0.176	0.18
F4	0.65	0.7	0.026	0.028
F5	0.62	0.67	0.024	0.026
F6	0.63	0.68	0.025	0.027
F7	0.7	0.8	0.028	0.031
F8	0.65	0.7	0.026	0.028
F9	0.62	0.67	0.024	0.026
F10	4.9	5	0.193	0.197
F11	4.46	4.56	0.176	0.18

For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).

7.3 Recommended Stencil Opening

7.4 Q5A Tape and Reel Information

Notes:

10-sprocket hole-pitch cumulative tolerance ±0.2.
Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
Material: black static-dissipative polystyrene.
All dimensions are in mm (unless otherwise specified).
A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.