CSD17571Q2 30V N-Channel NexFET Power MOSFETs
- SLPS393A October 2013 – January 2015 CSD17571Q2
  
  PRODUCTION DATA.

CSD17571Q2 30V N-Channel NexFET Power MOSFETs

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DATA SHEET

CSD17571Q2 30V N-Channel NexFET Power MOSFETs

1 Features

Low Q_g and Q_gd
Low Thermal Resistance
Avalanche Rated
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 2 mm × 2 mm Plastic Package

2 Applications

Optimized for Load Switch Applications
Storage, Tablets, and Handheld Devices
Optimized for Control FET Applications

3 Description

This 30 V, 20 mΩ, SON 2×2 NexFET™ power MOSFET is designed to minimize losses in power conversion and load management applications, while offering excellent thermal performance for the size of the package.

Top View

Product Summary

T_A = 25°C		TYPICAL VALUE		UNIT
V_DS	Drain-to-Source Voltage	30		V
Q_g	Gate Charge Total (4.5 V)	2.4		nC
Q_gd	Gate Charge Gate-to-Drain	0.6		nC
R_DS(on)	Drain-to-Source On-Resistance	V_GS = 4.5 V	24	mΩ
R_DS(on)	Drain-to-Source On-Resistance	V_GS = 10 V	20	mΩ
V_GS(th)	Threshold Voltage	1.6		V

Ordering Information⁽¹⁾

Device	Media	Qty	Package	Ship
CSD17571Q2	7-Inch Reel	3000	SON 2 x 2 mm Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C		VALUE	UNIT
V_DS	Drain-to-Source Voltage	30	V
V_GS	Gate-to-Source Voltage	±20	V
I_D	Continuous Drain Current (Package Limit)	22	A
I_D	Continuous Drain Current⁽¹⁾	7.6	A
I_DM	Pulsed Drain Current, T_A = 25°C⁽²⁾	39	A
P_D	Power Dissipation⁽¹⁾	2.5	W
T_J, T_stg	Operating Junction and Storage Temperature Range	–55 to 150	°C
E_AS	Avalanche Energy, single pulse I_D = 12 A, L = 0.1 mH, R_G = 25 Ω	7.2	mJ

R_θJA = 50 on 1 in² Cu (2 oz.) on 0.060" thick FR4 PCB
Pulse duration 10 μs, duty cycle ≤2%

R_DS(on) vs V_GS

Gate Charge

4 Revision History

Changes from * Revision (October 2013) to A Revision

Updated Figure #8Go

5 Specifications

5.1 Electrical Characteristics

T_A = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-Source Voltage	V_GS = 0 V, I_D = 250 μA	30			V
I_DSS	Drain-to-Source Leakage Current	V_GS = 0 V, V_DS = 24 V			1	μA
I_GSS	Gate-to-Source Leakage Current	V_DS = 0 V, V_GS = 20 V			100	nA
V_GS(th)	Gate-to-Source Threshold Voltage	V_DS = V_GS, I_DS = 250 μA	1.3	1.6	2	V
R_DS(on)	Drain-to-Source On-Resistance	V_GS = 4.5 V, I_DS = 5 A		24	29	mΩ
R_DS(on)	Drain-to-Source On-Resistance	V_GS = 10 V, I_DS = 5 A		20	24	mΩ
g_ƒs	Transconductance	V_DS = 15 V, I_DS = 5 A		43		S
DYNAMIC CHARACTERISTICS
C_ISS	Input Capacitance	V_GS = 0 V, V_DS = 15 V, ƒ = 1 MHz		360	468	pF
C_OSS	Output Capacitance			101	131	pF
C_RSS	Reverse Transfer Capacitance			9	12	pF
R_g	Series Gate Resistance			3.8	7.6	Ω
Q_g	Gate Charge Total (4.5 V)	V_DS = 15 V, I_DS = 5 A		2.4	3.1	nC
Q_gd	Gate Charge – Gate-to-Drain			0.6		nC
Q_gs	Gate Charge Gate-to-Source			0.9		nC
Q_g(th)	Gate Charge at V_th			0.6		nC
Q_OSS	Output Charge	V_DS = 15 V, V_GS = 0 V		3.4		nC
t_d(on)	Turn On Delay Time	V_DS = 15 V, V_GS = 4.5 V, I_DS = 5 A R_G = 2 Ω		5.3		ns
t_r	Rise Time			19		ns
t_d(off)	Turn Off Delay Time			8		ns
t_ƒ	Fall Time			2.6		ns
DIODE CHARACTERISTICS
V_SD	Diode Forward Voltage	I_DS = 5 A, V_GS = 0 V		0.8	1	V
Q_rr	Reverse Recovery Charge	V_DD = 15 V, I_F = 5 A, di/dt = 300 A/μs		2.3		nC
t_rr	Reverse Recovery Time	V_DD = 15 V, I_F = 5 A, di/dt = 300 A/μs		11		ns

5.2 Thermal Information

T_A = 25°C unless otherwise specified

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-Case Thermal Resistance⁽¹⁾			6.2	°C/W
R_θJA	Junction-to-Ambient Thermal Resistance⁽¹⁾⁽²⁾			65	°C/W

(1) R_θJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. R_θJC is specified by design, whereas R_θJA is determined by the user’s board design.

(2) Device mounted on FR4 material with 1 inch² (6.45 cm²), 2 oz. (0.071 mm thick) Cu.

Max R_θJA = 65 when mounted on 1 inch² (6.45 cm²) of 2 oz.
(0.071 mm thick) Cu.

Max R_θJA = 235 when mounted on minimum pad area of 2 oz.
(0.071 mm thick) Cu.

5.3 Typical MOSFET Characteristics

T_A = 25°C unless otherwise specified

Figure 1. Transient Thermal Impedance

Figure 2. Saturation Characteristics

Figure 4. Gate Charge

Figure 6. Threshold Voltage vs Temperature

Figure 8. Normalized On-State Resistance vs Temperature

Figure 10. Maximum Safe Operating Area

Figure 12. Maximum Drain Current vs Temperature

Figure 3. Transfer Characteristics

Figure 5. Capacitance

Figure 7. On-State Resistance vs Gate-to-Source Voltage

Figure 9. Typical Diode Forward Voltage

Figure 11. Single Pulse Unclamped Inductive Switching

6 Device and Documentation Support

6.1 Trademarks

NexFET is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

6.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

6.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.