CSD19535KTT 100-V N-Channel NexFET™ Power MOSFET
- SLPS539B March 2015 – January 2017 CSD19535KTT
  
  PRODUCTION DATA.

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DATA SHEET

CSD19535KTT 100-V N-Channel NexFET™ Power MOSFET

1 Features

Ultra-Low Q_g and Q_gd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
D²PAK Plastic Package

2 Applications

Hot Swap
Motor Control
Secondary Side Synchronous Rectifier

3 Description

This 100-V, 2.8 mΩ, D²PAK (TO-263) NexFET™ power MOSFET is designed to minimize losses in power conversion applications.

Pin Out

Product Summary

T_A = 25°C		TYPICAL VALUE		UNIT
V_DS	Drain-to-Source Voltage	100		V
Q_g	Gate Charge Total (10 V)	75		nC
Q_gd	Gate Charge Gate-to-Drain	11		nC
R_DS(on)	Drain-to-Source On Resistance	V_GS = 6 V	3.2	mΩ
R_DS(on)	Drain-to-Source On Resistance	V_GS = 10 V	2.8	mΩ
V_GS(th)	Threshold Voltage	2.7		V

Device Information⁽¹⁾

DEVICE	QTY	MEDIA	PACKAGE	SHIP
CSD19535KTT	500	13-Inch Reel	D²PAK Plastic Package	Tape and Reel
CSD19535KTTT	50	13-Inch Reel	D²PAK Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C		VALUE	UNIT
V_DS	Drain-to-Source Voltage	100	V
V_GS	Gate-to-Source Voltage	±20	V
I_D	Continuous Drain Current (Package Limited)	200	A
	Continuous Drain Current (Silicon Limited), T_C = 25°C	197
	Continuous Drain Current (Silicon Limited), T_C = 100°C	139
I_DM	Pulsed Drain Current⁽¹⁾	400	A
P_D	Power Dissipation, T_C = 25°C	300	W
T_J, T_stg	Operating Junction, Storage Temperature	–55 to 175	°C
E_AS	Avalanche Energy, Single Pulse I_D = 95 A, L = 0.1 mH	451	mJ

Max R_θJC = 0.5°C/W, pulse duration ≤ 100 µs, duty cycle ≤ 1%.

R_DS(on) vs V_GS

Gate Charge

4 Revision History

Changes from A Revision (May 2015) to B Revision

Added Receiving Notification of Documentation Updates section to Device and Documentation Support sectionGo
Changed the drawing in KTT Package Dimensions sectionGo
Changed the drawing in Recommended PCB Pattern sectionGo
Changed the drawing in Recommended Stencil Opening (0.125 mm Stencil Thickness) sectionGo

Changes from * Revision (March 2015) to A Revision

Added Community Resources Go

5 Specifications

5.1 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage	V_GS = 0 V, I_D = 250 μA	100			V
I_DSS	Drain-to-source leakage current	V_GS = 0 V, V_DS = 80 V			1	μA
I_GSS	Gate-to-source leakage current	V_DS = 0 V, V_GS = 20 V			100	nA
V_GS(th)	Gate-to-source threshold voltage	V_DS = V_GS, I_D = 250 μA	2.2	2.7	3.4	V
R_DS(on)	Drain-to-source on resistance	V_GS = 6 V, I_D = 100 A		3.2	4.1	mΩ
R_DS(on)	Drain-to-source on resistance	V_GS = 10 V, I_D = 100 A		2.8	3.4	mΩ
g_fs	Transconductance	V_DS = 10 V, I_D = 100 A		301		S
DYNAMIC CHARACTERISTICS
C_iss	Input capacitance	V_GS = 0 V, V_DS = 50 V, ƒ = 1 MHz		6100	7930	pF
C_oss	Output capacitance			1160	1510	pF
C_rss	Reverse transfer capacitance			29	38	pF
R_G	Series gate resistance			1.4	2.8	Ω
Q_g	Gate charge total (10 V)	V_DS = 50 V, I_D = 100 A		75	98	nC
Q_gd	Gate charge gate-to-drain			11		nC
Q_gs	Gate charge gate-to-source			25		nC
Q_g(th)	Gate charge at V_th			16		nC
Q_oss	Output charge	V_DS = 50 V, V_GS = 0 V		210		nC
t_d(on)	Turnon delay time	V_DS = 50 V, V_GS = 10 V, I_DS = 100 A, R_G = 0 Ω		9		ns
t_r	Rise time			18		ns
t_d(off)	Turnoff delay time			21		ns
t_f	Fall time			15		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage	I_SD = 100 A, V_GS = 0 V		0.9	1.1	V
Q_rr	Reverse recovery charge	V_DS= 50 V, I_F = 100 A, di/dt = 300 A/μs		435		nC
t_rr	Reverse recovery time	V_DS= 50 V, I_F = 100 A, di/dt = 300 A/μs		85		ns

5.2 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-case thermal resistance			0.5	°C/W
R_θJA	Junction-to-ambient thermal resistance			62	°C/W

5.3 Typical MOSFET Characteristics

T_A = 25°C (unless otherwise stated)

Figure 1. Transient Thermal Impedance

Figure 2. Saturation Characteristics

V_DS = 5 V

Figure 3. Transfer Characteristics

V_DS = 50 V

I_D = 100 A

Figure 4. Gate Charge

I_D = 250 µA

Figure 6. Threshold Voltage vs Temperature

I_D = 100 A

Figure 8. Normalized On-State Resistance vs Temperature

Single pulse, max R_θJC = 0.5°C/W

Figure 10. Maximum Safe Operating Area

Figure 12. Maximum Drain Current vs Temperature

Figure 5. Capacitance

Figure 7. On-State Resistance vs Gate-to-Source Voltage

Figure 9. Typical Diode Forward Voltage

Figure 11. Single Pulse Unclamped Inductive Switching