JAJSC77A May   2016  – March 2017 CSD19538Q3A

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4改訂履歴
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6デバイスおよびドキュメントのサポート
    1. 6.1 ドキュメントの更新通知を受け取る方法
    2. 6.2 コミュニティ・リソース
    3. 6.3 商標
    4. 6.4 静電気放電に関する注意事項
    5. 6.5 Glossary
  7. 7メカニカル、パッケージ、および注文情報
    1. 7.1 Q3Aパッケージの寸法
    2. 7.2 Q3Aの推奨PCBパターン
    3. 7.3 Q3Aの推奨ステンシル・パターン
    4. 7.4 Q3Aのテープ・アンド・リール情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Electrical Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 100 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 2.8 3.2 3.8 V
RDS(on) Drain-to-source on resistance VGS = 6 V, ID = 5 A 58 72 mΩ
VGS = 10 V, ID = 5 A 49 59
gfs Transconductance VDS = 10 V, ID = 5 A 6.1 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 50 V, ƒ = 1 MHz 349 454 pF
Coss Output capacitance 69 90 pF
Crss Reverse transfer capacitance 12.6 16.4 pF
RG Series gate resistance 4.6 9.2 Ω
Qg Gate charge total (10 V) VDS = 50 V, ID = 5 A 4.3 nC
Qgd Gate charge gate-to-drain 0.8 nC
Qgs Gate charge gate-to-source 1.6 nC
Qg(th) Gate charge at Vth 1 nC
Qoss Output charge VDS = 50 V, VGS = 0 V 12.3 nC
td(on) Turnon delay time VDS = 50 V, VGS = 10 V,
IDS = 5 A, RG = 0 Ω		 5 ns
tr Rise time 3 ns
td(off) Turnoff delay time 7 ns
tf Fall time 2 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 5 A, VGS = 0 V 0.85 1 V
Qrr Reverse recovery charge VDS= 50 V, IF = 5 A,
di/dt = 300 A/μs		 94 nC
trr Reverse recovery time 32 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 5.5 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 55 °C/W
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.

CSD19538Q3A m0161-01_lps202.gif
Max RθJA = 55°C/W when mounted on 1-in2 (6.45-cm2) of 2-oz (0.071-mm) thick Cu.
CSD19538Q3A m0161-02_lps202.gif
Max RθJA = 195°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)
CSD19538Q3A D001_SLPS583.png
Figure 1. Transient Thermal Impedance
CSD19538Q3A D002_SLPS583.gif
Figure 2. Saturation Characteristics
CSD19538Q3A D004_SLPS583.gif
ID = 5 A VDS = 50 V
Figure 4. Gate Charge
CSD19538Q3A D006_SLPS583.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD19538Q3A D008_SLPS583.gif
ID = 5 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD19538Q3A D010_SLPS583.gif
Single pulse, max RθJC = 5.5°C/W
Figure 10. Maximum Safe Operating Area
CSD19538Q3A D012_SLPS583_r2.gif
Figure 12. Maximum Drain Current vs Temperature
CSD19538Q3A D003_SLPS583.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD19538Q3A D005_SLPS583.gif
Figure 5. Capacitance
CSD19538Q3A D007_SLPS583.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD19538Q3A D009_SLPS583.gif
Figure 9. Typical Diode Forward Voltage
CSD19538Q3A D011_SLPS583.gif
Figure 11. Single Pulse Unclamped Inductive Switching