CSD87334Q3D Synchronous Buck NexFET™ Power Block
- SLPS546A July 2015 – March 2017 CSD87334Q3D
  
  PRODUCTION DATA.

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DATA SHEET

CSD87334Q3D Synchronous Buck NexFET™ Power Block

1 Features

Half-Bridge Power Block
Optimized for High-Duty Cycle
Up to 24 V_in
96.1% System Efficiency at 12 A
1.6-W P_Loss at 12 A
Up to 20-A Operation
High-Frequency Operation (up to 1.5 MHz)
High-Density SON 3.3 mm × 3.3 mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen-Free
Lead-Free Terminal Plating

2 Applications

Synchronous Buck Converters
- High-Frequency Applications
- High-Duty Cycle Applications
Synchronous Boost Converters
POL DC-DC Converters

3 Description

The CSD87334Q3D NexFET™ power block is an optimized design for synchronous buck and boost applications offering high-current, high-efficiency, and high-frequency capability in a small 3.3 mm × 3.3 mm outline. Optimized for 5-V gate drive applications, this product offers a flexible solution in high-duty cycle applications when paired with an external controller or driver.

TOP VIEW

Device Information⁽¹⁾

DEVICE	QTY	MEDIA	PACKAGE	SHIP
CSD87334Q3D	2500	13-Inch Reel	SON 3.30-mm × 3.30-mm Plastic Package	Tape and Reel
CSD87334Q3DT	250	7-Inch Reel	SON 3.30-mm × 3.30-mm Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Circuit

Typical Power Block Efficiency and Power Loss

4 Revision History

Changes from * Revision (August 2015) to A Revision

Changed T_G to T_GR minimum voltage, from –8 V : to –0.3 V in Absolute Maximum Ratings tableGo
Changed B_G to P_GND minimum voltage, from –8 V : to –0.3 V in Absolute Maximum Ratings tableGo
Changed I_GSS test condition for V_GS, from +10 / –8 V : to 10 V in Electrical Characteristics tableGo
Added Receiving Notification of Documentation Updates section and Community Resources section to Device and Documentation Support sectionGo

5 Specifications

5.1 Absolute Maximum Ratings

T_A = 25°C (unless otherwise noted) (see ⁽¹⁾)

			MIN	MAX	UNIT
	Voltage	V_IN to P_GND		30	V
		V_SW to P_GND		30
		V_SW to P_GND (10 ns)		32
		T_G to T_GR	–0.3	10
		B_G to P_GND	–0.3	10
I_DM	Pulsed current rating			60	A
P_D	Power dissipation			6	W
E_AS	Avalanche energy	Sync FET, I_D = 31 A, L = 0.1 mH		48	mJ
E_AS	Avalanche energy	Control FET, I_D = 31 A, L = 0.1 mH		48	mJ
T_J	Operating junction temperature		–55	150	°C
T_stg	Storage temperature		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

T_A = 25°C (unless otherwise noted)

			MIN	MAX	UNIT
V_GS	Gate drive voltage		3.3	8	V
V_IN	Input supply voltage			24	V
ƒ_SW	Switching frequency	C_BST = 0.1 µF (min)		1500	kHz
	Operating current			20	A
T_J	Operating temperature			125	°C

5.3 Power Block Performance

T_A = 25°C (unless otherwise noted) (see ⁽¹⁾)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS	Power loss⁽¹⁾	V_IN = 12 V, V_GS = 5 V, V_OUT = 3.3 V, I_OUT = 12 A, ƒ_SW = 500 kHz, L_OUT = 1 µH, T_J = 25°C		1.6		W
I_QVIN	V_IN quiescent current	T_G to T_GR = 0 V B_Gto P_GND = 0 V			10	µA

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins and using a high current 5-V driver IC.

5.4 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MAX	UNIT
R_θJA	Junction-to-ambient thermal resistance (min Cu)⁽²⁾	130	°C/W
R_θJA	Junction-to-ambient thermal resistance (max Cu)⁽²⁾⁽¹⁾	75	°C/W
R_θJC	Junction-to-case thermal resistance (top of package)⁽²⁾	21	°C/W
R_θJC	Junction-to-case thermal resistance (P_GND pin)⁽²⁾	2.1	°C/W

(1) Device mounted on FR4 material with 1-in² (6.45-cm²) Cu.

(2) R_θJC is determined with the device mounted on a 1-in² (6.45-cm²), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. R_θJC is specified by design while R_θJA is determined by the user’s board design.

5.5 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	Q1 CONTROL FET			Q2 SYNC FET			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-source voltage	V_GS = 0 V, I_DS = 250 µA	30			30			V
I_DSS	Drain-to-source leakage current	V_GS = 0 V, V_DS = 20 V			1			1	µA
I_GSS	Gate-to-source leakage current	V_DS = 0 V, V_GS = 10 V			100			100	nA
V_GS(th)	Gate-to-source threshold voltage	V_DS = V_GS, I_DS = 250 µA	0.75	0.90	1.20	0.75	0.90	1.20	V
R_DS(on)	Drain-to-source on resistance	V_GS = 3.5 V, I_DS = 12 A		6.3	8.3		6.3	8.3	mΩ
		V_GS = 4.5 V, I_DS = 12 A		5.6	7.0		5.6	7.0
		V_GS = 8 V, I_DS = 12 A		4.9	6.0		4.9	6.0
g_fs	Transconductance	V_DS = 15 V, I_DS = 12 A		62			62		S
DYNAMIC CHARACTERISTICS
C_ISS	Input capacitance	V_GS = 0 V, V_DS = 15 V, ƒ = 1 MHz		971	1260		971	1260	pF
C_OSS	Output capacitance			453	589		453	589	pF
C_RSS	Reverse transfer capacitance			16	21		16	21	pF
R_G	Series gate resistance			1.0	2.0		1.0	2.0	Ω
Q_g	Gate charge total (4.5 V)	V_DS = 15 V, I_DS = 12 A		6.4	8.3		6.4	8.3	nC
Q_gd	Gate charge gate-to-drain			1.0			1.0		nC
Q_gs	Gate charge gate-to-source			1.9			1.9		nC
Q_g(th)	Gate charge at V_th			0.9			0.9		nC
Q_OSS	Output charge	V_DS = 15 V, V_GS = 0 V		10.5			10.5		nC
t_d(on)	Turnon delay time	V_DS = 15 V, V_GS = 4.5 V, I_DS = 12 A, R_G = 2 Ω		4			4		ns
t_r	Rise time			7			7		ns
t_d(off)	Turnoff delay time			11			11		ns
t_f	Fall time			17			17		ns
DIODE CHARACTERISTICS
V_SD	Diode forward voltage	I_DS = 12 A, V_GS = 0 V		0.8	1.0		0.8	1.0	V
Q_rr	Reverse recovery charge	V_DS = 15 V, I_F = 12 A, di/dt = 300 A/µs		23			23		nC
t_rr	Reverse recovery Time	V_DS = 15 V, I_F = 12 A, di/dt = 300 A/µs		18			18		ns

Max R_θJA = 75°C/W when mounted on 1 in² (6.45 cm²) of 2-oz (0.071-mm) thick Cu.

Max R_θJA = 130°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

The typical power block system characteristic curves (Figure 1 through Figure 9) are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation for detailed explanation. Conditions for Figure 1 through Figure 5 are given by the following; V_IN = 12 V, V_GS = 5 V, V_OUT = 3.3 V, ƒ_SW = 500 kHz, L_OUT = 1 µH. T_A = 125°C, unless stated otherwise.

Figure 1. Power Loss vs Output Current

Figure 3. Safe Operating Area – PCB Horizontal Mount

Figure 5. Typical Safe Operating Area

Figure 2. Power Loss vs Temperature

Figure 4. Safe Operating Area – PCB Vertical Mount

V_IN = 12 V	V_GS = 5 V	V_OUT = 3.3 V
I_OUT = 15 A	L_OUT = 1.0 µH

Figure 6. Normalized Power Loss vs Switching Frequency

V_IN = 12 V	V_GS = 5 V	I_OUT = 15 A
ƒ_SW = 500 kHz	L_OUT = 1.0 µH

Figure 8. Normalized Power Loss vs Output Voltage

ƒ_SW = 500 kHz	V_GS = 5 V	V_OUT = 3.3 V
I_OUT = 15 A	L_OUT = 1.0 µH

Figure 7. Normalized Power Loss vs Input Voltage

V_IN = 12 V	V_GS = 5 V	I_OUT = 15 A
ƒ_SW = 500 kHz	V_OUT = 3.3 V

Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

T_A = 25°C, unless stated otherwise.

Figure 10. MOSFET Saturation Characteristics

I_D = 12 A	V_DS = 15 V

Figure 12. MOSFET Gate Charge

	I_D = 250 µA

Figure 14. MOSFET V_GS(th)

I_D = 12 A

Figure 16. MOSFET Normalized R_DS(on)

Figure 18. MOSFET Unclamped Inductive Switching

	V_DS = 5 V

Figure 11. MOSFET Transfer Characteristics

Figure 13. MOSFET Capacitance

Figure 15. MOSFET R_DS(on) vs V_GS

Figure 17. MOSFET Body Diode

6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

The CSD87334Q3D NexFET power block is an optimized design for synchronous buck applications using 5-V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-centric environment. System-level performance curves such as power loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application.

6.2 Typical Application

Figure 19. Typical Circuit Application

6.3 System Example

6.3.1 Power Loss Curves

MOSFET centric parameters such as R_DS(ON) and Q_gd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87334Q3D as a function of load current. This curve is measured by configuring and running the CSD87334Q3D as it would be in the final application (see Figure 19). The measured power loss is the CSD87334Q3D loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power loss = (V_IN × I_IN) + (V_DD × I_DD) – (V_{SW_AVG} × I_OUT)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions.

6.3.2 Safe Operating Area (SOA) Curves

The SOA curves in the CSD87334Q3D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the SOA. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

6.3.3 Normalized Curves

The normalized curves in the CSD87334Q3D data sheet provides guidance on the power loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of system conditions. The primary Y-axis is the normalized change in power loss, and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the SOA curve.

6.3.4 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example section). Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions.

6.3.4.1 Design Example

Operating conditions:

Output current = 15 A
Input voltage = 16 V
Output voltage = 5 V
Switching frequency = 1000 kHz
Inductor = 0.6 µH

6.3.4.2 Calculating Power Loss

Power loss at 15 A = 2.8 W (Figure 1)
Normalized power loss for input voltage ≈ 1.05 (Figure 7)
Normalized power loss for output voltage ≈ 1.08 (Figure 8)
Normalized power loss for switching frequency ≈ 1.03 (Figure 6)
Normalized power loss for output inductor ≈ 1.05 (Figure 9)
Final calculated power loss = 2.8 W × 1.05 × 1.08 × 1.03 × 1.05 ≈ 3.4 W

6.3.4.3 Calculating SOA Adjustments

SOA adjustment for input voltage ≈ 0.5°C (Figure 7)
SOA adjustment for output voltage ≈ 0.7°C (Figure 8)
SOA adjustment for switching frequency ≈ 0.3°C (Figure 6)
SOA adjustment for output inductor ≈ 0.5°C (Figure 9)
Final calculated SOA adjustment = 0.5 + 0.7 + 0.3 + 0.5 ≈ 2°C

In the design example, the estimated power loss of the CSD87334Q3D would increase to 3.4 W. In addition, the maximum allowable board or ambient temperature, or both, would have to decrease by 2°C. Figure 20 graphically shows how the SOA curve would be adjusted accordingly.

Start by drawing a horizontal line from the application current to the SOA curve.
Draw a vertical line from the SOA curve intercept down to the board or ambient temperature.
Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 2°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board or ambient temperature.

Figure 20. Power Block SOA

7 Layout

7.1 Layout Guidelines

7.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description on how to address each parameter is provided.

7.1.2 Electrical Performance

The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.

The placement of the input capacitors relative to the power block’s V_IN and P_GND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the V_IN and P_GND pins (see Figure 21). The example in Figure 21 uses six 10-µF ceramic capacitors (TDK C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8 should follow in order.
The driver IC should be placed relatively close to the power block gate pins. T_G and B_G should connect to the outputs of the driver IC. The T_GR pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, and so forth). The bootstrap capacitor for the driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the power block V_SW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.⁽¹⁾ In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R, and from 330 pf to 2200 pF for the C. Please refer to Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the V_SW node and P_GND (see Figure 21). ⁽¹⁾

^{Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla}

1. Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7.2 Layout Example

Figure 21. Recommended PCB Layout (Top Down)

7.3 Thermal Considerations

The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10-mil drill hole and a 16-mil capture pad.
Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the PCB design rules and manufacturing capabilities of the end user.