SLPS546A July   2015  – March 2017 CSD87334Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
    3. 6.3 System Example
      1. 6.3.1 Power Loss Curves
      2. 6.3.2 Safe Operating Area (SOA) Curves
      3. 6.3.3 Normalized Curves
      4. 6.3.4 Calculating Power Loss and SOA
        1. 6.3.4.1 Design Example
        2. 6.3.4.2 Calculating Power Loss
        3. 6.3.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Recommended PCB Design Overview
      2. 7.1.2 Electrical Performance
    2. 7.2 Layout Example
    3. 7.3 Thermal Considerations
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q3D Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Q3D Package Dimensions

CSD87334Q3D Q3D_Package_Dimensions.png
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A 0.850 1.050 0.033 0.041
b 0.280 0.400 0.011 0.016
b1 0.310 0.012
c 0.150 0.250 0.006 0.010
c1 0.150 0.250 0.006 0.010
d 0.940 1.040 0.037 0.041
d1 0.160 0.260 0.006 0.010
d2 0.150 0.250 0.006 0.010
d3 0.250 0.350 0.010 0.014
d4 0.175 0.275 0.007 0.011
D1 3.200 3.400 0.126 0.134
D2 2.650 2.750 0.104 0.108
E 3.200 3.400 0.126 0.134
E1 3.200 3.400 0.126 0.134
E2 1.750 1.850 0.069 0.073
e 0.650 TYP 0.026 TYP
L 0.400 0.500 0.016 0.020
θ 0.000 — — —
K 0.300 TYP 0.012 TYP

Table 1. Pinout Configuration

POSITION DESIGNATION
Pin 1 VIN
Pin 2 VIN
Pin 3 TG
Pin 4 TGR
Pin 5 BG
Pin 6 VSW
Pin 7 VSW
Pin 8 VSW
Pin 9 PGND

9.2 Land Pattern Recommendation

CSD87334Q3D M0193-01_LPS264.gif

NOTE:

Dimensions are in mm (in).

9.3 Stencil Recommendation

CSD87334Q3D M0207-01_LPS264.gif

NOTE:

Dimensions are in mm (in).

For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).

9.4 Q3D Tape and Reel Information

CSD87334Q3D m0144-01_lps202.gif

NOTES:

1. 10-sprocket hole-pitch cumulative tolerance ± 0.2.
 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
 3. Material: black static-dissipative polystyrene.
 4. All dimensions are in mm, unless otherwise specified.
 5. Thickness: 0.3 ± 0.05 mm.
 6. MSL1 260°C (IR and convection) PbF reflow compatible.