SLPS546A July   2015  – March 2017 CSD87334Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
    3. 6.3 System Example
      1. 6.3.1 Power Loss Curves
      2. 6.3.2 Safe Operating Area (SOA) Curves
      3. 6.3.3 Normalized Curves
      4. 6.3.4 Calculating Power Loss and SOA
        1. 6.3.4.1 Design Example
        2. 6.3.4.2 Calculating Power Loss
        3. 6.3.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Recommended PCB Design Overview
      2. 7.1.2 Electrical Performance
    2. 7.2 Layout Example
    3. 7.3 Thermal Considerations
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q3D Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted) (see (1))
MIN MAX UNIT
Voltage VIN to PGND 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to TGR –0.3 10
BG to PGND –0.3 10
IDM Pulsed current rating 60 A
PD Power dissipation 6 W
EAS Avalanche energy Sync FET, ID = 31 A, L = 0.1 mH 48 mJ
Control FET, ID = 31 A, L = 0.1 mH 48
TJ Operating junction temperature –55 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VGS Gate drive voltage 3.3 8 V
VIN Input supply voltage 24 V
ƒSW Switching frequency CBST = 0.1 µF (min) 1500 kHz
Operating current 20 A
TJ Operating temperature 125 °C

5.3 Power Block Performance

TA = 25°C (unless otherwise noted) (see (1))
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS Power loss(1) VIN = 12 V, VGS = 5 V, VOUT = 3.3 V,
IOUT = 12 A, ƒSW = 500 kHz,
LOUT = 1 µH, TJ = 25°C 		1.6 W
IQVIN VIN quiescent current TG to TGR = 0 V BG to PGND = 0 V 10 µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5-V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(2) 130 °C/W
Junction-to-ambient thermal resistance (max Cu)(2)(1) 75
RθJC Junction-to-case thermal resistance (top of package)(2) 21 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 2.1
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 CONTROL FET Q2 SYNC FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 30 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 µA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 10 V 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 0.75 0.90 1.20 0.75 0.90 1.20 V
RDS(on) Drain-to-source on resistance VGS = 3.5 V, IDS = 12 A 6.3 8.3 6.3 8.3 mΩ
VGS = 4.5 V, IDS = 12 A 5.6 7.0 5.6 7.0
VGS = 8 V, IDS = 12 A 4.9 6.0 4.9 6.0
gfs Transconductance VDS = 15 V, IDS = 12 A 62 62 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 971 1260 971 1260 pF
COSS Output capacitance 453 589 453 589 pF
CRSS Reverse transfer capacitance 16 21 16 21 pF
RG Series gate resistance 1.0 2.0 1.0 2.0 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
IDS = 12 A		 6.4 8.3 6.4 8.3 nC
Qgd Gate charge gate-to-drain 1.0 1.0 nC
Qgs Gate charge gate-to-source 1.9 1.9 nC
Qg(th) Gate charge at Vth 0.9 0.9 nC
QOSS Output charge VDS = 15 V, VGS = 0 V 10.5 10.5 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
IDS = 12 A, RG = 2 Ω		 4 4 ns
tr Rise time 7 7 ns
td(off) Turnoff delay time 11 11 ns
tf Fall time 17 17 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 12 A, VGS = 0 V 0.8 1.0 0.8 1.0 V
Qrr Reverse recovery charge VDS = 15 V, IF = 12 A,
di/dt = 300 A/µs		 23 23 nC
trr Reverse recovery Time 18 18 ns
CSD87334Q3D ThermalBoardMax.png
Max RθJA = 75°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD87334Q3D ThermalMin.png
Max RθJA = 130°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

The typical power block system characteristic curves (Figure 1 through Figure 9) are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation for detailed explanation. Conditions for Figure 1 through Figure 5 are given by the following; VIN = 12 V, VGS = 5 V, VOUT = 3.3 V, ƒSW = 500 kHz, LOUT = 1 µH. TA = 125°C, unless stated otherwise.
CSD87334Q3D D001_SLPS546.gif
Figure 1. Power Loss vs Output Current
CSD87334Q3D D003_SLPS546_r2.gif
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87334Q3D D005_SLPS546.gif
Figure 5. Typical Safe Operating Area
CSD87334Q3D D002_SLPS546.gif
Figure 2. Power Loss vs Temperature
CSD87334Q3D D004_SLPS546_r2.gif
Figure 4. Safe Operating Area – PCB Vertical Mount
CSD87334Q3D D006_SLPS546.gif
VIN = 12 V VGS = 5 V VOUT = 3.3 V
IOUT = 15 A LOUT = 1.0 µH
Figure 6. Normalized Power Loss vs Switching Frequency
CSD87334Q3D D008_SLPS546_r2.gif
VIN = 12 V VGS = 5 V IOUT = 15 A
ƒSW = 500 kHz LOUT = 1.0 µH
Figure 8. Normalized Power Loss vs Output Voltage
CSD87334Q3D D007_SLPS546.gif
ƒSW = 500 kHz VGS = 5 V VOUT = 3.3 V
IOUT = 15 A LOUT = 1.0 µH
Figure 7. Normalized Power Loss vs Input Voltage
CSD87334Q3D D009_SLPS546.gif
VIN = 12 V VGS = 5 V IOUT = 15 A
ƒSW = 500 kHz VOUT = 3.3 V
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87334Q3D D010_SLPS546_r2.gif
Figure 10. MOSFET Saturation Characteristics
CSD87334Q3D D012_SLPS546.gif
ID = 12 A VDS = 15 V
Figure 12. MOSFET Gate Charge
CSD87334Q3D D014_SLPS546_r2.gif
ID = 250 µA
Figure 14. MOSFET VGS(th)
CSD87334Q3D D016_SLPS546_r2.gif
ID = 12 A
Figure 16. MOSFET Normalized RDS(on)
CSD87334Q3D D018_SLPS546.gif
Figure 18. MOSFET Unclamped Inductive Switching
CSD87334Q3D D011_SLPS546.gif
VDS = 5 V
Figure 11. MOSFET Transfer Characteristics
CSD87334Q3D D013_SLPS546.gif
Figure 13. MOSFET Capacitance
CSD87334Q3D D015_SLPS546.gif
Figure 15. MOSFET RDS(on) vs VGS
CSD87334Q3D D017_SLPS546.gif
Figure 17. MOSFET Body Diode