SLPS426A December   2012  – February 2017 CSD87351ZQ5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Calculating Power Loss and SOA
        1. 6.2.1.1 Design Example
        2. 6.2.1.2 Calculating Power Loss
        3. 6.2.1.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q5D Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
PARAMETER CONDITIONS MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
TG to TGR –0.8 10
BG to PGND –8 10
IDM Pulsed current rating(2) 96 A
PD Power dissipation 12 W
EAS Avalanche energy Sync FET, ID = 87 A, L = 0.1 mH 378 mJ
Control FET, ID = 44 A, L = 0.1 mH 87
TJ Operating junction –55 150 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µs. Duty cycle ≤ 0.01%.

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
VGS Gate drive voltage 4.5 8 V
VIN Input supply voltage 27 V
ƒSW Switching frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating current 32 A
TJ Operating temperature 125 °C

5.3 Power Block Performance

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power loss(1) VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 20 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25°C 		2.5 W
IQVIN VIN quiescent current TG to TGR = 0 V
BG to PGND = 0 V 		10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(1)(2) 119 °C/W
Junction-to-ambient thermal resistance (max Cu)(1)(2) 62
RθJC Junction-to-case thermal resistance (top of package)(2) 25 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 2.3
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET
MIN TYP MAX MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 1.0 2.1 0.75 1.15 V
ZDS(on)(1) Effective AC on-impedance VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 20 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, 		7.4 1.6 mΩ
gfs Transconductance VDS = 15 V, IDS = 20 A 75 142 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 966 1255 2410 3133 pF
COSS Output capacitance 382 497 1130 1469 pF
CRSS Reverse transfer capacitance 19 25 45 59 pF
RG Series gate resistance 0.9 1.8 1 2 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
IDS = 20 A		 5.9 7.7 17 22 nC
Qgd Gate charge gate-to-drain 1.1 3.1 nC
Qgs Gate charge gate-to-source 2.1 3.7 nC
Qg(th) Gate charge at Vth 1.1 2 nC
QOSS Output charge VDS = 9.8 V, VGS = 0 V 6.5 23 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω		 6.1 7.7 ns
tr Rise time 16 10 ns
td(off) Turnoff delay time 10 31 ns
tf Fall time 2.1 4.2 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.86 1 0.78 1 V
Qrr Reverse recovery charge Vdd = 9.8 V, IF = 20 A,
di/dt = 300 A/μs		 8.6 23 nC
trr Reverse recovery time 16 24 ns
(1) Equivalent system performance based on application testing. See Application and Implementation section for details.

CSD87351ZQ5D M0189-01_LPS293.gif
Max RθJA = 62°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD87351ZQ5D M0190-01_LPS293.gif
Max RθJA = 119°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.

5.6 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise
CSD87351ZQ5D graph01_LPS287.png
Figure 1. Power Loss vs Output Current
CSD87351ZQ5D graph03_LPS287.png
Figure 3. Safe Operating Area – PCB Vertical Mount(1)1
CSD87351ZQ5D graph05_LPS287.png Figure 5. Typical Safe Operating Area(1)1
CSD87351ZQ5D graph02_LPS287.png
Figure 2. Normalized Power Loss vs Temperature
CSD87351ZQ5D graph04_LPS287.png
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)1
1. The typical power block system characteristic curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation section for detailed explanation.
CSD87351ZQ5D graph06_LPS287.png
Figure 6. Normalized Power Loss vs Switching Frequency
CSD87351ZQ5D graph08_LPS287.png
Figure 8. Normalized Power Loss vs Output Voltage
CSD87351ZQ5D graph07_LPS287.png
Figure 7. Normalized Power Loss vs Input Voltage
CSD87351ZQ5D graph09_LPS287.png
Figure 9. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise
CSD87351ZQ5D graph10_LPS287.png
Figure 10. Control MOSFET Saturation
CSD87351ZQ5D graph12_LPS287.png
Figure 12. Control MOSFET Transfer
CSD87351ZQ5D graph14_LPS287.png
Figure 14. Control MOSFET Gate Charge
CSD87351ZQ5D graph16_LPS287.png
Figure 16. Control MOSFET Capacitance
CSD87351ZQ5D graph18_LPS287.png
Figure 18. Control MOSFET VGS(th)
CSD87351ZQ5D graph20_LPS287.png
Figure 20. Control MOSFET RDS(on) vs VGS
CSD87351ZQ5D graph22_LPS287.png
Figure 22. Control MOSFET Normalized RDS(on)
CSD87351ZQ5D graph24_LPS287.png
Figure 24. Control MOSFET Body Diode
CSD87351ZQ5D graph26_LPS287.png
Figure 26. Control MOSFET Unclamped Inductive Switching
CSD87351ZQ5D graph11_LPS287.png
Figure 11. Sync MOSFET Saturation
CSD87351ZQ5D graph13_LPS287.png
Figure 13. Sync MOSFET Transfer
CSD87351ZQ5D graph15_LPS287.png
Figure 15. Sync MOSFET Gate Charge
CSD87351ZQ5D graph17_LPS287.png
Figure 17. Sync MOSFET Capacitance
CSD87351ZQ5D graph19_LPS287.png
Figure 19. Sync MOSFET VGS(th)
CSD87351ZQ5D graph21_LPS287.png
Figure 21. Sync MOSFET RDS(on) vs VGS
CSD87351ZQ5D graph23_LPS287.png
Figure 23. Sync MOSFET Normalized RDS(on)
CSD87351ZQ5D graph25_LPS287.png
Figure 25. Sync MOSFET Body Diode
CSD87351ZQ5D graph27_LPS287.png
Figure 27. Sync MOSFET Unclamped Inductive Switching