JAJSD34C April 2017 – April 2018 CSD88599Q5DC
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
In the Design Example – Regulate Current to Maintain Safe Operation section above, the estimated power loss of the CSD88599Q5DC would increase to 4.7 W. In addition, the maximum allowable board temperature would have to increase by 2.1°C. In Figure 21, the SOA graph was adjusted accordingly.
In this design example, the SOA board/ambient temperature adjustment yields a decrease of allowed junction temperature of 2.1°C from 122.2°C to 120.1°C. Now it is known that the intersection of the case and PCB temperatures on the TX line must stay below this point. For instance, if the power block case is observed operating at 124°C, the PCB temperature must in turn be kept under 118°C to maintain this crossover point.