SLPS416 Data sheet

SLPS416C June 2014 – March 2015 CSD95372AQ5M

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

DQP|12

サーマルパッド・メカニカル・データ

発注情報

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

T_A = 25°C (unless otherwise noted)

	MIN	MAX	UNIT
V_IN to P_GND	–0.3	25	V
V_SW to P_GND	–0.3	25	V
V_SW to P_GND (<10 ns)	–7	27	V
V_DD to P_GND	–0.3	7	V
ENABLE, PWM, FCCM, TAO to P_GND⁽²⁾	–0.3	V_DD + 0.3	V
BOOT to BOOT_R⁽²⁾	–0.3	V_DD + 0.3	V
P_D, Power Dissipation		12	W
T_J, Operating Temperature Range	–55	150	°C
T_stg, Storage Temperature Range	–55	150	°C

(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

(2) Should not exceed 7 V.

6.2 ESD Ratings

		VALUE		UNIT
ESD Rating	Human Body Model (HBM)	±2000		V
ESD Rating	Charged Device Model (CDM)	±500		V

6.3 Recommended Operating Conditions

T_A = 25° (unless otherwise noted)

			MIN	MAX	UNIT
V_DD	Gate Drive Voltage		4.5	5.5	V
V_IN	Input Supply Voltage			16	V
V_OUT	Output Voltage			5.5	V
I_OUT	Continuous Output Current	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.8 V, ƒ_SW = 500 kHz, L_OUT = 0.22 µH⁽¹⁾		60	A
I_OUT-PK	Peak Output Current⁽²⁾			90	A
ƒ_SW	Switching Frequency	C_BST = 0.1 µF (min)		2000	kHz
	On Time Duty Cycle	ƒ_SW = 1 MHz		85	%
	Minimum PWM On Time		20		ns
	Operating Temperature		–40	125	°C

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins.

(2) System conditions as defined in Note 1. Peak Output Current is applied for t_p = 50 µs.

6.4 Thermal Information

T_A = 25°C (unless otherwise noted)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-Case Thermal Resistance (Top of package)⁽¹⁾			15	°C/W
R_θJB	Junction-to-Board Thermal Resistance⁽²⁾			2	°C/W

(1) R_θJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches, 0.06 inch (1.52 mm) thick FR4 board.

(2) R_θJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

T_A = 25°C, V_DD = POR to 5.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS
	Power Loss⁽¹⁾	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.2 V, I_OUT = 30 A, ƒ_SW = 500 kHz, L_OUT = 0.22 µH , T_J = 25°C		3.3		W
	Power Loss⁽²⁾	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.2 V, I_OUT = 30 A, ƒ_SW = 500 kHz, L_OUT = 0.22 µH , T_J = 125°C		3.9		W
V_IN
I_Q	V_IN Quiescent Current	ENABLE = 0, V_DD = 5 V			10	µA
V_DD
I_DD	Standby Supply Current	ENABLE = 0, PWM = 0			250	µA
I_DD	Operating Supply Current	ENABLE = 5 V, PWM = 50% Duty cycle, ƒ_SW = 500 kHz		23		mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
V_DD Rising	Power-On Reset				3.9	V
V_DD Falling	UVLO		3.4			V
	Hysteresis		100		250	mV
	Startup Delay⁽³⁾	ENABLE = 5 V		6		µs
ENABLE
V_IH	Logic Level High	Schmitt Trigger Input See Figure 11	2.0			V
V_IL	Logic Level Low				0.8	V
	Weak Pulldown Impedance			100		kΩ
t_PDH	Rising Propagation Delay			3		µs
t_PDL	Falling Propagation Delay			30		ns
FCCM
V_IH	Logic Level High	Schmitt Trigger Input See Figure 13 and Figure 14	2.0			V
V_IL	Logic Level Low				0.8	V
	Weak Pullup Current			5		µA
THERMAL SHUTDOWN⁽²⁾
	Start Threshold		150	165		°C
	Temperature Hysteresis			25		°C
PWM
I_PWMH		PWM = 5 V		500		µA
I_PWML		PWM = 0		–500		µA
V_PWMH	PWM Logic Level High	C_PWM = 10 pF	2.3	2.5	2.7	V
V_PWML	PWM Logic Level Low		0.7	0.9	1.1	V
	PWM Tri-State Open Voltage			1.5		V
t_PDLH and t_PDHL	PWM to V_SW Propagation Delay⁽²⁾			50		ns
t_3HT	Tri-State Shutdown Hold-off Time ⁽²⁾			30		ns
t_3SD	Tri-State Shutdown Propagation Delay⁽²⁾			80	160	ns
t_3RD	Tri-State Recovery Propagation Delay⁽²⁾			50	80	ns
t_DEM	Diode Emulation Minimum On Time⁽²⁾			150		ns
BOOTSTRAP SWITCH
V_FBOOT	Forward Voltage	Measured from V_DD to V_BOOT, I_F = 10 mA		200	360	mV
I_RBOOT	Reverse Leakage⁽¹⁾	V_BOOT – V_DD = 20 V		0.15	1	µA
ZERO CROSSING COMPARATOR
	LS FET Turn-off Current	Diode Emulation Mode Enabled V_OUT = 1.8 V, L = 150 nH	0		1.125	A
THERMAL ANALOG OUTPUT TAO
	Output Voltage at 25°C		0.56	0.60	0.64	V
	Output Voltage Temperature Coefficient			8		mV/°C

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins.

(2) Specified by design

(3) POR to V_SW Rising

6.6 Typical Power Stage Characteristics

T_J = 125°C, unless stated otherwise. The typical CSD95372A system characteristic curves are based on measurements made on a PCB design with dimensions of 4 inches (W) x 3.5 inches (L) x 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. See the Application Information section for a detailed explanation.