SLPS446D April   2014  – December 2016 CSD95379Q3M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Functional Description
        1. 7.2.1.1 Powering CSD95379Q3M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 PWM Pin
      4. 7.2.4 SKIP# Pin
      5. 7.2.5 Zero Crossing (ZX) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Area (SOA) Curves
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss and SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Electrical Performance
      2. 9.1.2 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DNS|10
サーマルパッド・メカニカル・データ
発注情報

9 Layout

9.1 Layout Guidelines

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description on how to address each parameter follows.

9.1.1 Electrical Performance

The CSD95379Q3M has the ability to switch at voltage rates greater than 10 kV/µs. Take special care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD95379Q3M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 14). The example in Figure 14 uses 1 × 1-nF 0402 25-V and 3 × 10-µF 1206 25-V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power stage C8, C9, C10 and C11 should follow in order.
  • The bootstrap capacitor C7 0.1-µF 0603 16-V ceramic capacitor should be closely connected between BOOT and BOOT_R pins.
  • The switching node of the output inductor should be placed relatively close to the power stage CSD95379Q3M VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. (1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

1. Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

9.1.2 Thermal Performance

The CSD95379Q3M has the ability to use the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 14 uses vias with a 10-mil drill hole and a 16-mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

9.2 Layout Example

CSD95379Q3M layout_2.png Figure 14. Recommended PCB Layout (Top Down View)