SLPS446D April   2014  – December 2016 CSD95379Q3M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Functional Description
        1. 7.2.1.1 Powering CSD95379Q3M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 PWM Pin
      4. 7.2.4 SKIP# Pin
      5. 7.2.5 Zero Crossing (ZX) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Area (SOA) Curves
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss and SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Electrical Performance
      2. 9.1.2 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Drawing
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DNS|10
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Top View
CSD95379Q3M pinout_2.png

Pin Functions

PIN DESCRIPTION
NAME NUMBER
SKIP# 1 This pin enables the Diode Emulation function. When this pin is held low, Diode Emulation Mode is enabled for the sync FET. When SKIP# is high, the CSD95379Q3M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very-low power state.
VDD 3 Supply voltage to gate drivers and internal circuitry.
PGND 4 Power ground. Needs to be connected to pin 11 on the PCB.
VSW 5 Voltage switching node – pin connection to output inductor.
VIN 6 Input voltage pin. Connect input capacitors to close this pin.
BOOT_R 7 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V X5R, ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
BOOT 8
PWM 10 Pulse-width-modulated tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-state shutdown hold-off time (T3HT).
PGND 11 Power ground. Needs to be connected to pin 4 on the PCB.