SLPS542 January   2015 CSD97394Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powering CSD97394Q4M And Gate Drivers
      2. 8.3.2 Undervoltage Lockout Protection (UVLO)
      3. 8.3.3 PWM Pin
      4. 8.3.4 SKIP# Pin
        1. 8.3.4.1 Zero Crossing (ZX) Operation
      5. 8.3.5 Integrated Boost-Switch
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application Curves
  10. 10System Example
    1. 10.1 Power Loss Curves
    2. 10.2 Safe Operating Curves (SOA)
    3. 10.3 Normalized Curves
      1. 10.3.1 Calculating Power Loss and SOA
        1. 10.3.1.1 Design Example
        2. 10.3.1.2 Calculating Power Loss
        3. 10.3.1.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • DPC|8
サーマルパッド・メカニカル・データ
発注情報

7 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.2 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.4 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 3.0 W
VIN
IQ VIN quiescent current PWM = Floating, VDD = 5 V, VIN= 24 V 1 µA
VDD
IDD Standby supply current PWM = Float, SKIP# = VDD or 0 V 130 µA
SKIP# = Float 8 µA
IDD Operating supply current PWM = 50% Duty cycle, ƒSW = 500 kHz 5.3 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD Rising Power-on reset 4.15 V
VDD Falling UVLO 3.7 V
Hysteresis 0.2 mV
PWM AND SKIP# I/O SPECIFICATIONS
RI Input Impedance Pull up to VDD 1700 kΩ
Pull down (to GND) 800
VIH Logic level high 2.65 V
VIL Logic level low 0.6
VIH Hysteresis 0.2
VTS Tri-state voltage 1.3 2
tTHOLD(off1) Tri-state activation time (falling) PWM 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM 60
tTSKF Tri-state activation time (falling) SKIP# 1 µs
tTSKR Tri-state activation time (rising) SKIP# 1
t3RD(PWM) Tri-state exit time PWM (2) 100 ns
t3RD(SKIP#) Tri-state exit time SKIP#(2) 50 µs
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK Reverse leakage(2) VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design