JAJSAL1G May   2006  – June 2016 DAC082S085

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Feature Description
        1. 8.2.1.1 DAC Architecture
        2. 8.2.1.2 Output Amplifiers
        3. 8.2.1.3 Reference Voltage
        4. 8.2.1.4 Power-On Reset
    3. 8.3 Device Functional Modes
      1. 8.3.1 Power-Down Modes
    4. 8.4 Programming
      1. 8.4.1 Serial Interface
      2. 8.4.2 Input Shift Register
      3. 8.4.3 DSP and Microprocessor Interfacing
        1. 8.4.3.1 ADSP-2101/ADSP2103 Interfacing
        2. 8.4.3.2 80C51/80L51 Interface
        3. 8.4.3.3 68HC11 Interface
        4. 8.4.3.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Bipolar Operation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
        1. 12.1.1.1 仕様の定義
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DSC Package
10-Pin WSON
Top View
DGS Package
10-Pin VSSOP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 VA Supply Power supply input. Must be decoupled to GND.
2 VOUTA Analog Output Channel A analog output voltage.
3 VOUTB Analog Output Channel B analog output voltage.
4 NC — Not connected
5 NC — Not connected
6 GND Ground Ground reference for all on-chip circuitry.
7 VREFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND.
8 DIN Digital Input Serial data input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
9 SYNC Digital Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
10 SCLK Digital Input Serial clock input. Data is clocked into the input shift register on the falling edges of this pin.
PAD PAD Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.