JAJSAQ5F December   2007  – October 2016 DAC121C081 , DAC121C085

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifier
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Serial Interface
        1. 8.3.4.1 Basic I2C Protocol
        2. 8.3.4.2 Standard-Fast Mode
        3. 8.3.4.3 High-Speed (Hs) Mode
        4. 8.3.4.4 I2C Slave (Hardware) Address
      5. 8.3.5 Power-On Reset
      6. 8.3.6 Simultaneous Reset
      7. 8.3.7 Additional Timing Information: toutz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Writing to the DAC Register
      2. 8.5.2 Reading from the DAC Register
    6. 8.6 Registers
      1. 8.6.1 DAC Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
      2. 9.1.2 DSP/Microprocessor Interfacing
        1. 9.1.2.1 Interfacing to the 2-wire Bus
        2. 9.1.2.2 Interfacing to a Hs-mode Bus
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
        1. 12.1.1.1 仕様の定義
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

For best accuracy and minimum noise, the printed-circuit board containing the DAC121C081 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located on the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be used when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC121C081. Special care is required to ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces.

The DAC121C081 power supply should be bypassed with a 4.7-µF and a 0.1-µF capacitor as close as possible to the device with the 0.1 µF right at the device supply pin. The 4.7-µF capacitor should be a tantalum type and the 0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC121C081 should only be used for analog circuits.

Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. These clock and data lines should have controlled impedances.

Layout Example

DAC121C081 DAC121C085 layout_SNVS801.gif Figure 35. Layout Example