JAJSAQ5F December   2007  – October 2016 DAC121C081 , DAC121C085

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifier
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Serial Interface
        1. 8.3.4.1 Basic I2C Protocol
        2. 8.3.4.2 Standard-Fast Mode
        3. 8.3.4.3 High-Speed (Hs) Mode
        4. 8.3.4.4 I2C Slave (Hardware) Address
      5. 8.3.5 Power-On Reset
      6. 8.3.6 Simultaneous Reset
      7. 8.3.7 Additional Timing Information: toutz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Writing to the DAC Register
      2. 8.5.2 Reading from the DAC Register
    6. 8.6 Registers
      1. 8.6.1 DAC Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
      2. 9.1.2 DSP/Microprocessor Interfacing
        1. 9.1.2.1 Interfacing to the 2-wire Bus
        2. 9.1.2.2 Interfacing to a Hs-mode Bus
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの関連用語
        1. 12.1.1.1 仕様の定義
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

NGF Package
6-Pins WSON
Top View
DAC121C081 DAC121C085 wson_pkg_nas395.gif
DDC Package
6-Pin SOT
Top View
DAC121C081 DAC121C085 sot_pkg_nas395.gif
DGK Package
8-Pins VSSOP
Top View
DAC121C081 DAC121C085 vssop_pkg_nas395.gif

Pin Functions

PIN TYPE DESCRIPTION EQUIVALENT CIRCUIT
NAME WSON SOT VSSOP
ADR0 1 6 1 Digital Input,
three levels 		Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 and A0) of the 7-bit slave address. (see Table 1)
DAC121C081 DAC121C085 30004962.gif
ADR1 — — 2 Digital Input,
three levels		 Tri-state Address Selection Input. Sets Bits A6 and A3 of the 7-bit slave address. (see Table 1)
GND 4 3 5 Ground Ground for all on-chip circuitry —
SCL 2 5 3 Digital Input Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device.
DAC121C081 DAC121C085 30004961.gif
SDA 3 4 4 Digital
Input/Output		 Serial Data bi-directional connection. Data is clocked into or out of the internal 16-bit register relative to the clock edges of SCL. This is an open-drain data line that must be pulled to the supply (VA) by an external pullup resistor.
VOUT 6 1 8 Analog Output Analog Output Voltage —
VA 5 2 6 Supply Power supply input. For the SOT and WSON versions, this supply is used as the reference. Must be decoupled to GND. —
VREF — — 7 Supply Unbufferred reference voltage. For the VSSOP, this supply is used as the reference. VREF must be free of noise and decoupled to GND. —
PAD (LLP only) — — Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. —