JAJSM94B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
Synchronizing multiple DAC12DL3200 involves two synchronization functions as illustrated by Figure 7-21. The first is to synchronize the DACCLK clock domain in all DAC devices which includes clock dividers and FIFO outputs pointers. Secondly, the data clock domain (LVDS interface) must be synchronized using an input strobe signal from either the DxSTR input or LSB data lane of each bus (bit x, where x = [12 - LVDS_RESOLUTION]).Using the LSB eliminates the need for the DxSTR signals eliminating up to four LVDS pairs. Synchronization using DxSTR and LSB is described in Section 7.3.3.4.