JAJSM94B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
The list below is the startup procedure when using the LVDS input:
Start the DEVCLK
Apply power per the order in the power sequence section
Assert Reset
De-assert Reset – Fuse ROM load will automatically begin
Wait for Fuse ROM load to complete (FUSE_DONE=1)
Apply LVDS signals (and SYSREF if used) to inputs. This may have been done at any earlier point if desired, but must be stable by here.
Set DP_EN=1
Clear LVDS_CLK_ALM & STROBE_ALM
Synchronize the system
If using LVDS Strobes for alignment:
Set LVDS_STROBE_ALIGN=1
Wait for LVDS_STROBE_DET=1
If using SYSREF for alignment:
See SYSREF Windowing to enable and align synchronous SYSREF capturing.
Set SYSREF_ALIGN_EN=1
Wait for SYSREF_DET=1
Set SYSREF_ALIGN_EN=0
Configure FIFO_DLY (this may be done early but should be complete by here)
Clear all SYS_ALM bits
Wait for 100 DACCLK cycles for corrupted data to be flushed.
Enable Transmission using the TXENABLE pin or TXEN_A/B registers.