JAJSSV2G March 2011 – January 2024 DAC3482
PRODUCTION DATA
The byte-wide format is selected by setting 16bit_in to 0b in the config2 register. In this mode the 16-bit data for channels I and Q is byte-wide interleaved in the form I0[15:8], I0[7:0], Q0[15:8], Q0[7:0], I1[15:8]… into the D[7:0] 8-bit bus. Data into the DAC3482 is formatted according to the diagram shown in Figure 6-4 where index 0 is the data LSB and index 15 is the data MSB. A rising edge transition of the sync signal, either FRAME or SYNC, is used to establish the correct sample boundaries.