JAJSSV2G March 2011 – January 2024 DAC3482
PRODUCTION DATA
The DAC3482 input FIFO can be completely bypassed through registers config0 and config32. The register configuration for each mode is described in Table 6-3.
Register | Control Bits |
config0 | fifo_ena |
config32 | syncsel_fifoout(3:0) |
FIFO MODE | config0 and config32 FIFO Bits | ||||
---|---|---|---|---|---|
fifo_ena | syncsel_fifoout | ||||
BIT 3: sif_sync | BIT 2: OSTR | BIT 1: FRAME | BIT 0: SYNC | ||
Dual Sync Sources | 1 | 0 | 1 | 0 | 0 |
Single Sync Source | 1 | 0 | 0 | 1 or 0 Depends on the sync source | 1 or 0 Depends on the sync source |
Bypass | 0 | X | X | X | X |