JAJSSV2G March 2011 – January 2024 DAC3482
PRODUCTION DATA
Register Name | Address | Bit | Name | Function | Default Value |
---|---|---|---|---|---|
config24 | 0x18 | 15:13 | Reserved | Reserved for factory use. | 001 |
12 | pll_reset | When set, the PLL loop filter (LPF) is pulled down to 0 V. Toggle from 1b to 0b to restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the process is fast, the supplies are higher than nominal, ... resulting in the feedback dividers missing a clock. | 0 | ||
11 | pll_ndivsync_ena | When set, the LVDS SYNC input is used to sync the PLL N dividers. | 1 | ||
10 | pll_ena | When set, the PLL is enabled. When cleared, the PLL is bypassed. | 0 | ||
9:8 | Reserved | Reserved for factory use. | 00 | ||
7:6 | pll_cp(1:0) | PLL pump charge select 00: No charge pump 01: Single pump charge 10: Not used 11: Dual pump charge | 00 | ||
5:3 | pll_p(2:0) | PLL pre-scaler dividing module control. 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 000: 8 | 001 | ||
2:0 | pll_lfvolt(2:0) | PLL loop filter voltage. This three bit read-only indicator has step size of 0.4125 V. The entire range covers from 0 V to 3.3 V. The optimal lock range of the PLL will be from 010 to 101 (for example, 0.825 V to 2.063 V). Adjust pll_vco(5:0) for optimal lock range. | NA |