JAJSSV2G March 2011 – January 2024 DAC3482
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG OUTPUT(1) | |||||||
ts(DAC) | Output settling time to 0.1% | Transition: Code 0x0000 to 0xFFFF | 10 | ns | |||
tpd | Output propagation delay | DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below). | 2 | ns | |||
tr(IOUT) | Output rise time 10% to 90% | 220 | ps | ||||
tf(IOUT) | Output fall time 90% to 10% | 220 | ps | ||||
Digital latency | 8-bit interface |
No interpolation, FIFO enabled, Mixer off, QMC off, Inverse sinc off | 250 | DAC clock cycles | |||
2x Interpolation | 212 | ||||||
4x Interpolation | 372 | ||||||
8x Interpolation | 723 | ||||||
16x Interpolation | 1440 | ||||||
16-bit interface |
No interpolation, FIFO enabled, Mixer off, QMC off, Inverse sinc off | 140 | |||||
2x Interpolation | 228 | ||||||
4x Interpolation | 417 | ||||||
8x Interpolation | 817 | ||||||
16x Interpolation | 1630 | ||||||
Fine mixer | 24 | ||||||
QMC | 32 | ||||||
Inverse sinc | 36 | ||||||
Power-up Time |
DAC wake-up time | IOUT current settling to 1% of IOUTFS from output sleep | 2 | µs | |||
DAC sleep time | IOUT current settling to less than 1% of IOUTFS in output sleep | 2 |