JAJSSV2G March 2011 – January 2024 DAC3482
PRODUCTION DATA
STEP | READ/WRITE | ADDRESS | VALUE | DESCRIPTION |
---|---|---|---|---|
1 | N/A | N/A | N/A | Set TXENABLE Low |
2 | N/A | N/A | N/A | Power-up the device |
3 | N/A | N/A | N/A | Apply LVPECL DACCLKP/N for PLL reference clock |
4 | N/A | N/A | N/A | Toggle RESETB pin |
5 | Write | 0x00 | 0xA19E | QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled, clock divider sync enabled, inverse sinc filter enabled. |
6 | Write | 0x01 | 0x040E | Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision). Note: bit8 = 0b |
7 | Write | 0x02 | 0xF052 | Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision. Mixer block with NCO enabled, 2s-complement. Word wide interface. |
8 | Write | 0x03 | 0xA000 | Output current set to 20-mA FS with internal reference and 1.28-kΩ RBIAS resistor. |
9 | Write | 0x07 | 0xD8FF | Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the Alarm output. |
10 | Write | 0x08 | N/A | Program the desired channel I QMC offset value. (Causes Auto-Sync for QMC Offset Block) |
11 | Write | 0x09 | N/A | Program the desired FIFO offset value and channel Q QMC offset value. |
12 | Write | 0x0C | N/A | Program the desired channel I QMC gain value. |
13 | Write | 0x0D | N/A | Coarse mixer mode not used. Program the desired channel Q QMC gain value. |
14 | Write | 0x10 | N/A | Program the desired channel IQ QMC phase value. (Causes Auto-Sync QMC Correction Block) Note : bit 13 and bit 12 = 1b |
15 | Write | 0x12 | N/A | Program the desired channel IQ NCO phase offset value. (Causes Auto-Sync for Channel IQ NCO Mixer) |
16 | Write | 0x14 | 0x2000 | Program the desired channel IQ NCO frequency value |
17 | Write | 0x15 | 0x0000 | Program the desired channel IQ NCO frequency value |
18 | Write | 0x18 | 0x2C67 | PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler = 4. |
19 | Write | 0x19 | 0x20F4 | M = 32, N = 16, PLL VCO bias tune = 01b |
20 | Write | 0x1A | 0xEC00 | PLL VCO coarse tune = 59 |
21 | Write | 0x1B | 0x0800 | Internal reference |
22 | Write | 0x1E | 0x9191 | QMC offset IQ and QMC correction IQ can be synced by sif_sync or auto-sync from register write |
23 | Write | 0x1F | 0x4140 | Mixer IQ values synced by SYNCP/N. NCO accumulator synced by SYNCP/N. FIFO data formatter synced by FRAMEP/N. |
24 | Write | 0x20 | 0x2400 | FIFO Input Pointer Sync Source = FRAME FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR |
25 | N/A | N/A | N/A | Provide all the LVDS DATA and DATACLK Provide rising edge FRAMEP/N and rising edge SYNCP/N to sync the FIFO input pointer and PLL N-dividers. |
26 | Read | 0x18 | N/A | Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in 0x1A. |
27 | Write | 0x05 | 0x0000 | Clear all alarms in 0x05. |
28 | Read | 0x05 | N/A | Read back all alarms in 0x05. Check for PLL lock, FIFO collision, DACCLK-gone, DATACLK-gone, .... Fix the error appropriately. Repeat step 26 and 27 as necessary. |
29 | Write | 0x1F | 0x4142 | Sync all the QMC blocks using sif_sync. These blocks can also be synced via auto-sync through appropriate register writes. |
30 | Write | 0x00 | 0xA19A | Disable clock divider sync. |
31 | Write | 0x1F | 0x4148 | Disable FIFO data formatter sync. Set sif_sync to 0b for the next sif_sync event. |
32 | Write | 0x20 | 0x0000 | Disable FIFO input and output pointer sync. |
33 | Write | 0x18 | 0x2467 | Disable PLL N-dividers sync. |
34 | N/A | N/A | N/A | Set TXENABLE high. Enable data transmission. |