SLAS749E March   2011  – November 2015 DAC3484

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal InformationZAY package information to Thermal InformationTJ row from top of thermal table
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements - Digital Specifications
    9. 6.9  Switching Characteristics - AC Specifications
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
        1. 7.3.2.1 Word-Wide Format
        2. 7.3.2.2 Byte-Wide Format
      3. 7.3.3  Input FIFO
      4. 7.3.4  FIFO Modes of Operation
        1. 7.3.4.1 Dual Sync Sources Mode
        2. 7.3.4.2 Single Sync Source Mode
        3. 7.3.4.3 Bypass Mode
      5. 7.3.5  Clocking Modes
        1. 7.3.5.1 PLL Bypass Mode
        2. 7.3.5.2 PLL Mode
      6. 7.3.6  FIR Filters
      7. 7.3.7  Complex Signal Mixer
        1. 7.3.7.1 Full Complex Mixer
        2. 7.3.7.2 Coarse Complex Mixer
        3. 7.3.7.3 Mixer Gain
        4. 7.3.7.4 Real Channel Upconversion
      8. 7.3.8  Quadrature Modulation Correction (QMC)
        1. 7.3.8.1 Gain and Phase Correction
        2. 7.3.8.2 Offset Correction
        3. 7.3.8.3 Group Delay Correction
      9. 7.3.9  Temperature Sensor
      10. 7.3.10 Data Pattern Checker
      11. 7.3.11 Parity Check Test
        1. 7.3.11.1 Word-by-Word Parity
        2. 7.3.11.2 Block Parity
      12. 7.3.12 DAC3484 Alarm Monitoring
      13. 7.3.13 LVPECL Inputs
      14. 7.3.14 LVDS Inputs
      15. 7.3.15 Unused LVDS Port Termination
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Assembly
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from D Revision (September 2015) to E Revision

  • Changed I(CLKVDD) Clock supply current Mode 1 max value from 95mA to 100mAGo

Changes from C Revision (August 2012) to D Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
  • Added 196-ball 12x12mm BGA package to DescriptionGo
  • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization.Go
  • Added additional circuit configuration for unused terminals - IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/NGo
  • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization.Go
  • Changed DACCLKP/N Differential voltage TYP value from 1.0 V to 0.8 V Go
  • Changed the parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level. Go
  • Changed OSTRP/N Differential voltage TYP value from 1.0 V to 0.8 V Go
  • Changed the parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level. Go
  • Changed Standard high swing note for Electrical Characteristics – Digital SpecificationsGo
  • Added Minimum voltage note for Electrical Characteristics – Digital Specifications Go
  • Added LMK0480x family to note for Timing Requirements – Digital Specifications Go
  • Added text to Input FIFO section Go
  • Changed syncsel_fifoout(3:0) description in Input FIFO section to clarify the FIFO read pointer reset capture method and limitation.Go
  • Added Note to Input FIFO section Go
  • Added LMK0480x family to Input FIFO section Go
  • Changed text in Single Sync Source Mode to clarify the latency limitation of Single Sync Source ModeGo
  • Added the effect of bypassing the FIFO in the Bypass Mode section to clarify the operation of the FIFO, LVDS FRAME, and LVDS SYNC in FIFO Bypass Mode. Go
  • Added package information for LPF pin in PLL Mode sectionGo
  • Changed table reference in FIR Filters section Go
  • Added text to Data Pattern Checker section with additional operating recommendations. Go
  • Added reference to application report in DAC3484 Alarm Monitoring sectionGo
  • Added note to Figure 80 Go
  • Added Unused LVDS Port Termination sectionGo
  • Changed information to Multi-Device Operation: Single Sync Source mode section to clarify the latency limitation of Single Sync Source Mode.Go
  • Changed Figure 90 to clarify the latency limitation of Single Sync Source Mode. Go
  • Changed the NCO setting description in the Example Start-up Sequence Section to reflect the example register writes.Go
  • Added A32 to A32 for DAC3484IRKD and N9 for DAC3484IZAY in register config3 bit 0 descriptionGo
  • Changed alarm_lparity to alarm_fparity in register config7 Go
  • Changed QMC offset registers to QMC correction registers in register config16Go
  • Added SLEEP pin information to register config27 bit 11 Go
  • Changed 1.2VDIG to DIGVDD in register config27 bits 5:0Go
  • Changed 1.2VCLK to CLKVDD in register config27 bits 5:0Go
  • Added pin description for both packages in register config35 Go
  • Added reference to Digital Input Timing Specifications Table in register config36Go
  • Added text to register config45 bit 0 descriptionGo

Changes from B Revision (February) to C Revision

  • Added thermal information to the Absolute Maximum Ratings tableGo
  • Added Recommended Operating Conditions tableGo
  • Deleted TJ row from top of thermal tableGo
  • Deleted OPERATING RANGE section from bottom of Electrical Characteristics – DC Specifications tableGo

Changes from A Revision (July 2011) to B Revision

  • Changed the revision from A, July 2011 to B, June 2012Go
  • Changed Package options in FEATURESGo
  • Added ZAY packageGo
  • Added ZAY pin functionsGo
  • Added ZAY package information to Thermal InformationGo
  • Added Input Common Mode max value of 1.6VGo
  • Added information to CLOCK INPUT (DACCLKP/N) in Electrical Characteristics – Digital SpecificationsGo
  • Added information to OUTPUT STROBE (OSTRP/N) in Electrical Characteristics – Digital SpecificationsGo
  • Changed Electrical Characteristics – AC Specifications AC Performance informationGo
  • Changed Figure 21Go
  • Changed Figure 22Go
  • Changed Figure 23Go
  • Added Figure 48Go
  • Added Figure 49Go
  • Changed config 3 to config9 in Input FIFO sectionGo
  • Added information for double-charge-pump current to PLL MODE sectionGo
  • Changed Figure 71Go
  • Changed +3.75 to –3.75 degrees in 1024 steps to +26.5 to –26.5 degrees in 4096 steps in GAIN AND PHASE CORRECTION sectionGo
  • Added dual channel mode enable information to POWER-UP SEQUENCE step 6.Go
  • Changed config1, bit 8 in Table 11Go
  • Changed config16, bits 13:12 in Table 11Go
  • Changed register config1, bit8 from Reserved to quad_enaGo
  • Changed register config16, bits 13:12 from reserved to dual_ena (1:0)Go

Changes from * Revision (March 2011) to A Revision

  • Changed from PRODUCT PREVIEW to PRODUCTION DATAGo