JAJSCY6B February 2017 – July 2017 DAC38RF86 , DAC38RF87 , DAC38RF96 , DAC38RF97
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | C11, C12, D11, E11, F12, J12, K11, L11, M11, M12, D12, L12 | - | Analog ground. |
ALARM | K8 | O | CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via RESET_CONFIG alm_out_pol control bit. |
AMUX0 | G3 | O | Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating. |
AMUX1 | F3 | O | Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating. |
ATEST | C8 | O | Analog test pin for DAC, references and PLL. Can be left floating. |
CLKTX+ | A7 | O | Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal. |
CLKTX- | A6 | O | Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal. |
DACCLK+ | A10 | I | Device clock, internal 100 Ω differential termination, self-biased, positive terminal. |
DACCLK- | A9 | I | Device clock, internal 100 Ω differential termination, self-biased, negative terminal. |
DACCLKSE | A12 | I | Single ended device clock optional input. Can be left floating if not used. internal 50 Ω termination. |
DGND | A2, B2, C2, D2, D6, E2, E7, F2, F6, G2, G7, H6, J7, K2, L2, L3, L4, L5, M6 | - | Digital ground. |
EXTIO | C10 | Requires a 0.1 μF decoupling capacitor to AGND. | |
GPI0 | L6 | Factory use only. User should GND. | |
GPI1 | M7 | Factory use only. User should GND. | |
GPO0 | L7 | Used for CMOS SYNC0\ signal. | |
GPIO1 | K7 | Used for CMOS SYNC1\ signal. | |
IFORCE | D3 | Test pin for on chip parametrics. Can be left floating. | |
RBIAS | C9 | I/O | Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS (8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output. |
RESET | K9 | I | Active low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up. |
RX0+ | J1 | I | CML SerDes interface lane 0 input, positive |
RX0- | K1 | I | CML SerDes interface lane 0 input, negative |
RX1+ | M1 | I | CML SerDes interface lane 1 input, positive |
RX1- | L1 | I | CML SerDes interface lane 1 input, negative |
RX2+ | M2 | I | CML SerDes interface lane 2 input, positive |
RX2- | M3 | I | CML SerDes interface lane 2 input, negative |
RX3+ | M5 | I | CML SerDes interface lane 3 input, positive |
RX3- | M4 | I | CML SerDes interface lane 3 input, negative |
RX4+ | H1 | I | CML SerDes interface lane 4 input, positive |
RX4- | G1 | I | CML SerDes interface lane 4 input, negative |
RX5+ | E1 | I | CML SerDes interface lane 5 input, positive |
RX5- | F1 | I | CML SerDes interface lane 5 input, negative |
RX6+ | D1 | I | CML SerDes interface lane 6 input, positive |
RX6- | C1 | I | CML SerDes interface lane 6 input, negative |
RX7+ | A1 | I | CML SerDes interface lane 7 input, positive |
RX7- | B1 | I | CML SerDes interface lane 7 input, negative |
SCLK | L9 | I | Serial interface clock. Internal pull-down. |
SDEN | M8 | I | Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up. |
SDIO | M10 | I/O | Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal pull-down. |
SDO | M9 | O | Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default). |
SLEEP | L8 | I | Active high asynchronous hardware power-down input. Internal pull-down. |
SYNC0+ | C4 | O | Synchronization request to transmitter for JESD204B link 0, LVDS positive output. |
SYNC0- | C3 | O | Synchronization request to transmitter for JESD204B link 0, LVDS negative output. |
SYNC1+ | C7 | O | Synchronization request to transmitter for JESD204B link 1, LVDS positive output. |
SYNC1- | C6 | O | Synchronization request to transmitter for JESD204B link 1, LVDS negative output. |
SYSREF+ | A3 | I | LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization. |
SYSREF- | A4 | I | LVPECL SYSREF negative input, internal 100 Ω differential termination, self biased. (See the SYSREF+ description) |
TCLK | K4 | I | JTAG test clock. Internal pull-down |
TDI | H4 | I | JTAG test data in. Internal pull-up |
TDO | J4 | O | JTAG test data out. Internal pull-up |
TESTMODE | K3 | I | This pin is used for factory testing. Recommended to connect to ground. |
TMS | K5 | I | JTAG test mode select. Internal pull-up |
TRST | J5 | I | JTAG test reset. Must be connected to ground if not used. Internal pull-up |
TXENABLE | K6 | I | Transmit enable active high input. Internal pull-down. This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission. To enable analog output data transmission, pull the CMOS TXENABLE pin to high. To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. |
VDDA1 | F11, J11 | I | Analog 1V supply voltage. Must be separated from VDDDIG1 for best performance. |
VDDA18 | G11, H11 | I | Analog 1.8V supply voltage. (1.8 V) |
VDDPLL1 | D8, E8 | I | Analog 1V supply for PLL. |
VDDAPLL18 | B9, B10 | I | PLL analog supply voltage. (1.8 V) |
VDDAVCO18 | D9, E9 | I | Analog supply voltage for VCO (1.8 V) |
VDDCLK1 | G9, H9 | I | Internal clock buffer supply voltage (1 V) It is recommended to isolate this supply from VDDDIG1 and VDDA1. |
VDDL1_1 | G8, H8 | I | DAC core supply voltage. (1 V) |
VDDL2_1 | G10, H10 | I | DAC core supply voltage. (1 V) |
VDDDIG1 | A5, B5, C5, D5, D7, E3, E4, E5, E6, F4, F5, G4, G5 | I | Digital supply voltage. (1 V) It is recommended to isolate this supply from VDDCLK1 and VDDA1. |
VDDE1 | F7, H7, G6, J6 | I | Digital Encoder supply voltage (1 V). Must be separated from VDDDIG1 for best performance. |
VDDIO18 | H5 | I | Supply voltage for all digital I/O and CMOS I/O. (1.8 V) |
VDDOUT18 | G12, H12 | I | DAC supply voltage (1.8 V) |
VDDR18 | H2, J2 | I | Supply voltage for SerDes. (1.8 V) |
VDDS18 | B3, B4 | I | Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8V) |
VDDT1 | H3, J3 | I | Supply voltage for SerDes termination. (1 V) |
VDDTX1 | B6 | I | Supply voltage for divided clock output. (1 V) |
VDDTX18 | B7 | I | Supply voltage for divided clock output. (1.8 V) |
VEE18N | D10, E10, K10, L10 | I | Analog supply voltage. (-1.8 V) |
VOUT1 | K12 | O | DAC channel 1 single ended output. |
VOUT2 | E12 | O | DAC channel 2 single ended output. |
VSENSE | D4 | I | Test pin for on chip parametrics. Can be left floating. |
VSSCLK | A8, A11, B8, B11, B12, F8, F9, F10, J8, J9, J10 | - | Clock ground. |