JAJSS39A November 2023 – March 2024 DAC39RF10EF , DAC39RFS10EF
PRODUCTION DATA
A data descrambler is available in the DAC device to descramble the data after reception. Scrambling is used to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler is optional for 8b/10b encoded mode, however it is mandatory for 64b/66b encoded mode to have sufficient spectral content for clock recovery and adaptive equalization. The scrambler operates on the data before encoding, such that the 8b/10b scrambler scrambles the 8-bit octets before 10-bit encoding and the 64b/66b scrambler scrambles the 64-bit block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically synchronizes its descrambler to the incoming scrambled data stream. For 8b/10b encoding, the initial lane alignment sequence (ILAS) is never scrambled. The descrambler can be enabled by setting SCR for 8b/10b encoding mode, but it is automatically enabled in 64b/66b mode. The scrambling polynomial is different for 8b/10b encoding and 64b/66b encoding schemes as defined by the JESD204C standard.