There are many critical signal connections that require specific care and attention during PC board design:

1. DAC analog output signals
2. Sampling clock
3. Serdes (JESD204x) data inputs
4. Power supplies
5. Power and grounding strategy

There are many considerations to take note of when developing a high-speed PCB design. Here are a few recommendations and example figures to follow for any high-speed PCB design:

1. Route using loosely coupled 100-Ω differential traces when possible on the Serdes inputs. This routing minimizes impact of corners and length-matching serpentines on pair impedance.
2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential traces. Tightly coupled differential traces can be used to reduce self-radiated noise or to improve neighboring trace noise immunity when adequate spacing cannot be provided.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or poorly connected ground pours.
4. Use smoothly radiused corners and avoid 45- or 90-degree bends to reduce impedance mismatches on all high-speed inputs/outputs for both analog and digital signal traces. See Figure 8-23 as an example.
   Figure 8-23 Radius Corner and Stitch Vias next to High_Speed Signal Trace
5. Incorporate any ground plane cutouts necessary at component landing pads, ie – SMA connectors, baluns, etc., to avoid impedance discontinuities at these locations. Cut-outs below these landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50-Ω, single-ended impedance. See Figure 8-24 and Figure 8-25 as an examples.
   Figure 8-24 Ground Cut-outs below Balun and Bias-T Pins
   Figure 8-25 Ground Cut-out Below SMA Connector Center Pin
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the ground plane or ground plane clearances associated with power and signal vias and through-hole component leads.
7. Provide symmetrically located ground tie stitching vias adjacent to any high-speed signal at an appropriate spacing as determined by the maximum frequency the trace transports (λ/4). See Figure 8-23 as an example.
8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place two ground vias (“return vias”) close to critical high-speed signal trace via when transitioning between layers to provide a nearby ground return path. See Figure 8-26 and Figure 8-27 as examples.
   Figure 8-26 Return Vias for High Speed Clock
   Figure 8-27 Return Vias for High Speed Clock Near Clock Generator
9. Pay particular attention to potential coupling between JESD204x data input routing and the analog output routing. Switching noise from the JESD204x inputs can couple into the analog output traces and show up as wideband noise due to the high bandwidth of the DAC. Route the Serdes JESD204x data inputs on a separate layer, if possible, from the DAC output traces to avoid noise coupling, see Figure 8-28 and Figure 8-29 as examples.
   Figure 8-28 Serdes Top Layer Routing with Ground Fill Isolation
   Figure 8-29 Serdes Bottom Layer Routing with Ground Isolation
10. A reduction in the clock amplitude can degrade the DAC noise performance, so make sure the clock signal has adequate drive strength, especially for high frequencies. To help avoid this, keep the clock source close to the DAC if using a passive balun to drive or interface with the sampling clock pins of the converter. If trace routes are longer than a few inches, impedance matching at the DAC’s sampling clock input pins can be necessary.

Examples of the power plane design is show in Figure 8-30 through Figure 8-33.

Figure 8-30 Power Plane Layout for Layer 3

Figure 8-31 Power Plane Layout for Layer 5

Figure 8-32 Power Plane Layout for Layer 12

Figure 8-33 Power Plane Layout for Layer 14

In addition, TI recommends the following general PCB fabrication considerations for all high-speed PCB designs:

1. Use high quality dielectric materials for any critical signal layers within the PCB stack-up. Typically, the top and bottom layers are the most critical and more board houses can implement a mix of high and standard quality dielectrics, also known as a hybrid stack-up.
2. Use multiple power layers if necessary to provide a robust power delivery system to the converter.
3. Use multiple ground/power/ground layer stacks within the PCB to develop high frequency decoupling within the PCB itself, it is recommended these layers are 4mils or less.
4. Use a solid ground plane, do not split or “slot” the ground plane to create an analog vs. digital grounding barrier or divider. This typically causes more harm than good.