JAJSTV7 March   2024 DAC39RF10-SEP , DAC39RF10-SP , DAC39RFS10-SEP , DAC39RFS10-SP

PRODMIX  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Power Dissipation and Supply Currents
    16. 6.16 Typical Characteristics: Linearity Sweeps
    17. 6.17 Typical Characteristics: Modulated Waveforms
    18. 6.18 Typical Characteristics: Phase and Amplitude Noise
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
      7. 8.1.7 Radiation Environment Recommendations
        1. 8.1.7.1 SPI Programming
        2. 8.1.7.2 JESD204C Reliability
        3. 8.1.7.3 NCO Reliability
          1. 8.1.7.3.1 NCO Frequency and Phase Correction (Strategy #1)
          2. 8.1.7.3.2 NCO Frequency Correction (Strategy No. 2)
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

SPI Register Map

Table 7-45 lists the SPI registers. All register offset addresses not listed in Table 7-45 should be considered as reserved locations and the register contents should not be modified. Reserved register fields in addresses with non-reserved R/W fields always return the default/reset value during read, not the written value.

Table 7-45 SPI Registers
OffsetAcronymRegister NameSection
0x0000CONFIG_AConfiguration AGo
0x0002DEVICE_CONFIGDevice Configuration Go
0x0003CHIP_TYPEChip TypeGo
0x0004CHIP_IDChip IdentificationGo
0x0006CHIP_VERSIONChip VersionGo
0x000CVENDOR_IDVendor Identification Go
0x0010-0x007FRESERVED
0x0080SYSREF_CTRLSYSREF ControlGo
0x0081-0x008FRESERVED
0x0090-0x0092SYSREF_POSSYSREF Capture PositionGo
0x0093-0x009FRESERVED
0x00A0SYSREF_ALIGNSYSREF Alignment ControlGo
0x00A1SYSREF_TERMSYSREF Termination ConfigurationGo
0x00A2-0x00FFRESERVED
0x0100JESD_ENJESD204C Subsystem EnableGo
0x0101JMODEJESD204C ModeGo
0x0102JESD_MJESD204C Number of Streams Go
0x0103JCTRLJESD204C ControlGo
0x0104SHMODEJESD204C Sync Word ModeGo
0x0105KM1JESD204C K ParameterGo
x0106RBDJESD204C Release Buffer DelayGo
0x0107JESD_STATUSJESD204C System Status RegisterGo
0x0108REFDIVJESD204C Reference DividerGo
0x0109MPYJESD204C PLL MultiplierGo
0x010ARATEJESD204C Receive RateGo
0x010BLB_VRANGEJESD204C VCO RangeGo
0x010C-0x011FRESERVED
0x0120JSYNC_NJESD204C Manual Sync RequestGo
0x0121JTESTJESD204C Test ControlGo
0x0122-0x0123RESERVEDRESERVED
0x0124JTIMERJESD204C Watchdog TimerGo
0x0125-0x0126RESERVED
0x0127SYNC_EPWJESD204C SYNC Error Report Pulse WidthGo
0x0128CRC_THJESD204C CRC Error ThresholdsGo
0x0129-0x012BRESERVED
0x012CLANE_ARSTATLane Arrival StatusGo
0x012DRESERVED
0x012E-0x012FLANE_INVPHY Lane InversionGo
0x0130-0x013FLANE_SEL[15:0]PHY Lane Select for Logical Lane nGo
0x0140-0x014FLANE_ARR[15:0]Lane n Arrival TimeGo
0x0150-0x015FLANE_STATUS[15:0]Lane n StatusGo
0x0160-0x016FLANE_ERR[15:0]Lane n Error FlagsGo
0x0170-0x017FFIFO_STATUS[15:0]Gearbox FIFO Status for Logical Lane nGo
0x0180-0x0189RESERVED
0x018A-0x019FRESERVED
0x01A0BER_ENBER Measurement ControlGo
0x01A1-0x01AFRESERVED
0x01B0-0x01BFBER_CNT[15:0]BER Error Count for Lane nGo
0x01C0RESERVED
0x01C1JPHY_CTRLSerDes PHY ControlGo
0x01C2EQ_CTRLSerDes Equalizer ControlGo
0x01C3EQZEROSerDes Equalizer ZeroGo
0x01D0-0x01DFLANE_EQ[15:0]SerDes Equalizer Level for Lane nGo
0x01E0-0x01EFLANE_EQS[15:0]SerDes Equalizer Status for Lane nGo
0x1F0ESRUNSerDes Eye-Scan Run ControlGo
0x01F1ES_CTRLSerDes Eye-Scan Control Go
0x01F2ESPOSerDes Eye-Scan Phase OffsetGo
0x01F3ESVOSerDes Eye-Scan Voltage OffsetGo
0x01F4ES_BIT_SELECTSerDes Eye-Scan Bit Select Go
0x01F5ESCOUNT_CLRSerDes Error Counter ClearGo
0x01F6-0x01F7ESDONESerDes Eye-Scan Process DoneGo
0x01F8-0x01FFRESERVED
0x0200-0x020FESVO_S[15:0]SerDes Eye-Scan Voltage Offset for Lane nGo
0x0210-0x022FECOUNT[15:0]SerDes Error/Mismatch Count for Lane nGo
0x0230-0x0233RESERVED
0x0234LOS_THSerDes Loss-of_Signal ThresholdGo
0x0235EQCNTSZSerDes Equalizer Counter SizeGo
0x0236-0x237RESERVED
0x0238CDRLOCKSerDes CDR Lock/FreezeGo
0x0239CDRPHASESerDes CDR Phase StatusGo
0x023A-0x024FRESERVED
0x0250PLL_STATUSSerDes PLL StatusGo
0x0251-0x0252RESERVED
0x0253JESD_RSTJESD ResetGo
0x0254-0x02AFRESERVED
0x02B0EXTREF_ENEnable External ReferenceGo
0x02B1CUR_2X_ENDAC Current Doubler EnableGo
0x02B2-0x02C1RESERVED
0x02C2-0x02CERESERVED
0x02CFDAC_OFS_CHG_BLKDAC Offset Adjustment Change BlockGo
0x02D0-0x02DFRESERVED
0x02E0DP_ENDatapath EnableGo
0x02E1DUC_LDUC Interpolation FactorGo
0x02E2DUC_GAINDUC GainGo
0x02E3DUC_FORMATDUC Output FormatGo
0x02E4DAC_SRCDAC SourceGo
0x02E5-0x02E7RESERVED
0x02E8MXMODEDAC Output ModeGo
0x02E9RESERVED
0x02EATRUNC_HLSBTruncation Half LSB OffsetGo
0x02EB-0x02F7RESERVED
0x02F8TX_EN_SELTransmitter Enable Control SelectionGo
0x02F9TX_ENTransmitter Enable ConfigurationGo
0x02FA-0x02FFRESERVED
0x0300NCO_CTRLNCO ControlGo
0x0301NCO_CONTNCO Phase Continuous ModeGo
0x0302NCO_SYNCNCO Synchronization ConfigurationGo
0x0303NCO_ARNCO Accumulator ResetGo
0x0304SPI_SYNCSPI SyncGo
0x0305NCO_SSNCO Continuous Self-Sync ModeGo
0x0306-0x0317RESERVED
0x0318-0x031FAMP[3:0]DDS AmplitudeGo
0x0320-0x0327FREQ[0]Frequency for NCO0 AccumulatorGo
0x0328-0x032FFREQ[1]Frequency for NCO1 AccumulatorGo
0x0330-0x0337FREQ[2]Frequency for NCO2 AccumulatorGo
0x0338-0x033FFREQ[3]Frequency for NCO3 AccumulatorGo
0x0340-0x0347PHASE[3:0]Phase for NCOn AccumulatorGo
0x0348-0x0377RESERVED
0x0378-0x037FAMP_R[3:0]Readback for Amplitude Workd for NCOnGo
0x0380-0x039FFREQ_R[3:0]Readback for Frequency for NCOn AccumulatorGo
0x03A0-0x03A7PHASE_R[3:0]Readback for Phase Word for NCOn AccumulatorGo
0x03A8-0x03DFRESERVED
0x03E0FR_FRS_RReadback for FR SynchronizationGo
0x03E1FR_NCO_AR_RReadback for FR NCO Accumulator ResetGo
0x03E2-0x03FFRESERVED
0x0400TS_TEMPTempeature Reading in CelsiusGo
0x0401TS_SLEEPTemperature Sensor SleepGo
0x0402-0x040FRESERVED
0x0410SYNC_STATUSSynchronization StatusGo
0x0411-0x042FRESERVED
0x0430SYS_ALMSystem Alarm StatusGo
0x0431ALM_MASKAlarm MaskGo
0x0432MUTE_MASKDAC Mute MaskGo
0x0433MUTE_RECDAC Mute RecoveryGo
0x0434-0x05FFRESERVED
0x0600FUSE_STATUSFuse StatusGo
0x0601-0x0722RESERVED
0x0723FINE_CUR_AFine Bias Current Control for DACAGo
0x0724COARSE_CUR_ACoarse Bias Current Control for DACAGo
0x0725FINE_CUR_BFine Bias Current Control for DACBGo
0x0726COARSE_CUR_BCoarse Bias Current Control for DACBGo
0x0727DEM_ADJDEM AdjustGo
0x0728RESERVED
0x0729DEM_DITHDEM and DITHER ControlGo
0x72A-0x072DDAC_OFSDAC_Offset_AdjustmentGo
0x72E - 0x7FFRESERVED

7.5.3.1 CONFIG_A Register (Offset = 0h) [reset = 30h]

CONFIG_A is shown in Figure 7-61 and described in Table 7-46.

Return to the Register Summary Table.

Configuration A (default: 0x30)

Figure 7-61 CONFIG_A Register
76543210
SOFT_RESETRESERVEDASCENDRESERVEDRESERVED
R/W-0hR/W-0hR/W-1hR/W-1hR/W-0h
Table 7-46 CONFIG_A Register Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0hWriting a 1 to this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing and will always read zero. After writing this bit, the part may take up to 5 ns to reset. During this time, do not perform any SPI transactions.
6RESERVEDR/W0h
5ASCENDR/W1h0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)
4RESERVEDR1hAlways read 1.
3-0RESERVEDR/W0h

7.5.3.2 DEVICE_CONFIG Register (Offset = 2h) [reset = 00h]

DEVICE_CONFIG is shown in Figure 7-62 and described in Table 7-47.

Return to the Register Summary Table.

Device Configuration (default: 0x00)

Figure 7-62 DEVICE_CONFIG Register
76543210
RESERVEDMODE
R/W-0hR/W-0h
Table 7-47 DEVICE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1-0MODER/W0h

0 : Normal operation (default)

1 : Reserved

2 : Reserved

3 : Full power down. The user should follow the recommendations in Section 8.1.6 in this mode to avoid reliability concerns.

7.5.3.3 CHIP_TYPE Register (Offset = 3h) [reset = 04h]

CHIP_TYPE is shown in Figure 7-63 and described in Table 7-48.

Return to the Register Summary Table.

Chip Type (read-only: 0x04)

Figure 7-63 CHIP_TYPE Register
76543210
RESERVEDCHIP_TYPE
R/W-0hR-4h
Table 7-48 CHIP_TYPE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0CHIP_TYPER4hAlways returns 0x4, indicating that the part is a high speed DAC.

7.5.3.4 CHIP_ID Register (Offset = 4h) [reset = 003Bh]

CHIP_ID is shown in Figure 7-64 and described in Table 7-49.

Return to the Register Summary Table.

Chip Identification (read-only)

Figure 7-64 CHIP_ID Register
15141312111098
CHIP_ID
R-0h
76543210
CHIP_ID
R-3Bh
Table 7-49 CHIP_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0CHIP_IDR003BhAlways returns 0x003B indicating it is the DAC39RF10 device family

7.5.3.5 CHIP_VERSION Register (Offset = 6h) [reset = 02h]

CHIP_VERSION is shown in Figure 7-65 and described in Table 7-50.

Return to the Register Summary Table.

Chip Version (read-only)

Figure 7-65 CHIP_VERSION Register
76543210
CHIP_VERSION
R-2h
Table 7-50 CHIP_VERSION Register Field Descriptions
BitFieldTypeResetDescription
7-0CHIP_VERSIONR02h

1: PG1.0

2: PG2.0

7.5.3.6 VENDOR_ID Register (Offset = Ch) [reset = 0451h]

VENDOR_ID is shown in Figure 7-66 and described in Table 7-51.

Return to the Register Summary Table.

Vendor Identification (default: 0x0451)

Figure 7-66 VENDOR_ID Register
15141312111098
VENDOR_ID
R-04h
76543210
VENDOR_ID
R-51h
Table 7-51 VENDOR_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0VENDOR_IDR451hTI vendor ID

7.5.3.7 SYSREF_CTRL Register (Offset = 0080h) [reset = 40h]

SYSREF_CTRL is shown in Figure 7-67 and described in Table 7-52.

Return to the Register Summary Table.

SYSREF Control

Figure 7-67 SYSREF_CTRL Register
76543210
SYSREF_PROC_ENSYSREF_RECV_SLEEPSYSREF_PS_ENSYSREF_ZOOMSYSREF_SEL
R/W-0bR/W-1bR/W-0bR/W-0bR/W-0h
Table 7-52 SYSREF_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7SYSREF_PROC_ENR/W0h When set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always clear SYSREF_RECV_SLEEP before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital.
6SYSREF_RECV_SLEEPR/W1bClear this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before setting this bit.
5SYSREF_PS_ENR/W0bWhen set, SYSREF_POS will contain 1’s for all positions that have been detected as near the SYSREF edge since this bit was set. When cleared, SYSREF_POS will only contain 1’s for the last SYSREF edge that was detected.
4SYSREF_ZOOMR/W0bSet this bit to “zoom” in the SYSREF strobe status (impacts SYSREF_POS and the step size of SYSREF_SEL).
3-0SYSREF_SELR/W0bSet this field to select which SYSREF delay to use. Set this based on the results returned by SYSREF_POS.

7.5.3.8 SYSREF_POS Register (Offset = 90h) [reset = NA]

SYSREF_POS is shown in Figure 7-68 and described in Table 7-53.

Return to the Register Summary Table.

SYSREF Position Capture

Figure 7-68 SYSREF_POS Register
2322212019181716
RESERVEDSYSREF_POS
RR
15141312111098
SYSREF_POS
R
76543210
SYSREF_POS
R
Table 7-53 SYSREF_POS Register Field Descriptions
BitFieldTypeResetDescription
23-20ReservedR0x0Reserved
19-0SYSREF_POSRNAReturns a 20-bit status value that indicates the position of the SYSREF edge with respect to CLK. Use this to determine the proper programming for SYSREF_SEL, and SYSREF_ZOOM.

7.5.3.9 SYSREF_ALIGN Register (Offset = 00A0h) [reset = 00h]

SYSREF_ALIGN is shown in Figure 7-69 and described in Table 7-54.

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SYSREF Alignment Control

Figure 7-69 SYSREF_ALIGN Register
76543210
RESERVEDSYSREF_ALIGN_EN
R/W-00hR/W-0b
Table 7-54 SYSREF_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00hReserved
0SYSREF_ALIGN_ENR/W0bWhen this bit is set, the chip realigns to each detected SYSREF edge. This affects both the external clock divider and the JESD subsystem.

SYSREF_TERM Register (Offset = 00A1h) [reset = 00h]

SYSREF_TERM is shown in Figure 7-70 and described in Table 7-55.

Return to the Register Summary Table.

SYSREF Termination Configruation

Figure 7-70 SYSREF_TERM Register
76543210
RESERVEDSYSREF_RECV_LVPECL
R/W-00hR/W-0b
Table 7-55 SYSREF_TERM Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00hReserved
0SYSREF_RECV_LVPECLR/W0b

0: SYSREF termination is 100 Ohm differential with Vcm of 0.4V

1: SYSREF termination is singled ended 50 Ohm to GND (LVPECL mode)

7.5.3.10 JESD_EN Register (Offset = 0100h) [reset = 00h]

JESD_EN is shown in Figure 7-71 and described in Table 7-56.

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JESD204C Subsystem Enable

Figure 7-71 JESD_EN Register
76543210
RESERVEDJESD_EN
R/W-00hR/W-0b
Table 7-56 JESD_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0JESD_ENR/W0b

0 : Disable JESD204C interface

1 : Enable JESD204C interface

When JESD_EN=0, the JESD204C subsystem is held in reset and the SERDES PHY is disabled. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.

Note: This register should only be changed when DP_EN=0.

7.5.3.11 JMODE Register (Offset = 0101h) [reset = 00h]

JMODE is shown in Figure 7-72 and described in Table 7-57.

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JESD204C Mode

Figure 7-72 JMODE Register
76543210
RESERVEDJMODE
R/W-00bR/W-000000b
Table 7-57 JMODE Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00b
5-0JMODERW000000b

Specify the JESD204C interface mode. See Table 7-22.

Note: This register should only be changed when JESD_EN=0.

7.5.3.12 JESD_M Register (Offset = 0102h) [reset = 01h]

JESD_M is shown in Figure 7-73 and described in Table 7-58.

Return to the Register Summary Table.

JESD204C Number of Streams

Figure 7-73 JESD_M Register
76543210
JESD_M
R/W-0hR/W-1h
Table 7-58 JESD_M Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0JESD_MR/W1h

Specify the number of sample streams to enable (JESD204C M parameter). The supported settings for JESD_M depend on the DUC interpolation (DUC_L) and Mx.

LDUC: Supported Settings for JESD_M

1x: 1 or 2 (but never larger than Mx)

2x or 3x: 2 (but never larger than Mx)

4x or 6x: 2 or 4 (but never larger than Mx)

8x or higher:2, 4, 6 or 8 (but never larger than Mx)

See Table 7-22 for the Mx value associated with each JMODE. The number of lanes enabled (L) is computed as: L=ceiling(M/Mx*Lx). An I/Q pair counts as two streams. For example, when inputting 4 IQ streams, program JESD_M=8.

Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

7.5.3.13 JCTRL Register (Offset = 0103h) [reset = 03h]

JCTRL is shown in Figure 7-74 and described in Table 7-59.

Return to the Register Summary Table.

JESD204C Control. This register should only be changed when JESD_EN = 0.

Figure 7-74 JCTRL Register
76543210
RESERVEDTI_MODESUBCLASSJENCRESERVEDSFORMATSCR
R/W-0bR/W-0bR/W-0bR/W-0bR/W-00bR/W-1bR/W-1b
Table 7-59 JCTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0b
6TI_MODER/W0b

0 : JESD204C standard mode (default)

1 : TI Mode - set this when using TI FPGA transmitter IP

5SUBCLASSR/W0b

Specify how the elastic buffer is released:

0 : Subclass 0 operation (default). Release the elastic buffer immediately once all lanes have starting writing to the buffer.

1 : Subclass 1 operation. Release the elastic buffer on a release opportunity defined by the LMFC/LEMC and RBD.

4JENCR/W0b

0 : Use 8b/10b link layer

1 : Use 64b/66b link layer

3-2RESERVEDR/W0b
1SFORMATR/W1b

Input sample format for JESD204C samples

0 : Offset binary

1 : Signed 2’s complement (default)

0SCRR/W1b

0 : 8b/10b Scrambler disabled

1 : 8b/10b Scrambler enabled (default)

The 8b/10b scrambler is recommended to improve spurious noise and make sure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. This register has no effect on 64b/66b modes (which are always scrambled).

7.5.3.14 SHMODE Register (Offset = 0104h) [reset = 00h]

SHMODE is shown in Figure 7-75 and described in Table 7-60.

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JESD204C Sync Word Mode

Figure 7-75 SHMODE Register
76543210
RESERVEDSHMODE
R/W-0bR/W-00b
Table 7-60 SHMODE Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W00h
1-0SHMODER/W00b

Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JENC=1 (64b/66b mode).

0 : Enable CRC-12 checking (JESD204C Table 41) (default setting)

1 : RESERVED

2 : RESERVED

3 : RESERVED

Note: This device does not support any JESD204C command features. All command fields are ignored by the receiver.

Note: This register should only be changed when JESD_EN=0.

7.5.3.15 KM1 Register (Offset = 0105h) [reset = 1Fh]

KM1 is shown in Figure 7-76 and described in Table 7-61.

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JESD204C K Parameter (minus 1)

Figure 7-76 KM1 Register
76543210
KM1
R/W-1Fh
Table 7-61 KM1 Register Field Descriptions
BitFieldTypeResetDescription
7-0KM1R/W1Fh

K is the number of frames per multiframe, and K-1 shall be programmed here when using the 8b/10b link layer (see JENC). Depending on the JMODE setting, there are constraints on the legal values of K (see Table 7-22 and KR). Programming an illegal value for K will cause the link to malfunction.

The default value is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is ignored. The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN=0.

7.5.3.16 RBD Register (Offset = 106h) [reset = 00h]

RBD is shown in Figure 7-77 and described in Table 7-62.

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JESD204C Release Buffer Delay

Figure 7-77 RBD Register
76543210
RESERVEDRBD
R/W-0bR/W-000000b
Table 7-62 RBD Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00b
5-0RBDR/W000000b

This register shifts the elastic buffer release opportunities. Increasing RBD by 1 delays the release opportunities by 4 bytes (octets).

The legal RBD range is 0 to K*F/4-1.

For 64b/66b modes, the legal RBD range is 0 to 63.

See Programming RBD.

Note: This register should only be changed when JESD_EN=0.

7.5.3.17 JESD_STATUS Register (Offset = 0107h) [reset = NA]

JESD_STATUS is shown in Figure 7-78 and described in Table 7-63.

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JESD204C / System Status

Figure 7-78 JESD_STATUS Register
76543210
EB_ERRLINK_UPJSYNC_STATEREALIGNEDALIGNEDPLL_LOCKEDRESERVED
R/W1CRRR/W1CRRR
Table 7-63 JESD_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7EB_ERRR/W1CNA

Elastic buffer experienced underflow/overflow. Check RBD.

Write a 1 to clear this bit.

6LINK_UPRNA

When set, indicates that the JESD204C link is up (elastic buffer released).

5JSYNC_STATERNA

Returns the state of the JESD204C SYNC signal.

0 : SYNC asserted

1 : SYNC de-asserted

4REALIGNEDR/W1CNA

When any clock dividers or the LMFC/LEMC counters are realigned by SYSREF, this bit gets set. Write a 1 to clear this bit.

The behavior of this bit is undefined when SUBCLASS=0.

3ALIGNEDRNA

When set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (including the LMFC/LEMC). This bit is read-only (cannot be cleared via SPI). After JESD_EN is set, the part may require up to 7 SYSREF pulses to achieve full alignment and set this bit.

The behavior of this bit is undefined when SUBCLASS=0.

2PLL_LOCKEDRNAWhen high, indicates that all enabled SerDes PLLs are locked.
1-0RESERVEDRNA

7.5.3.18 REFDIV Register (Offset = 0108h) [reset = 30h]

REFDIV is shown in Figure 7-79 and described in Table 7-64.

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JESD204C Reference Divider

Figure 7-79 REFDIV Register
76543210
RESERVEDREFDIV
R/W-0bR/W-30h
Table 7-64 REFDIV Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00b
5-0REFDIVR/W30h

Specifies the frequency divisor to generate the PHY PLL reference clock (FREF) from the DAC clock (FCLK). See PLL Control.

The following values are legal: 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48. All other values are reserved and produce undefined behavior.

7.5.3.19 MPY Register (Offset = 0109h) [reset = 14h]

MPY is shown in Figure 7-80 and described in Table 7-65.

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JESD204C PLL Multiplier

Figure 7-80 MPY Register
76543210
MPY
R/W-14h
Table 7-65 MPY Register Field Descriptions
BitFieldTypeResetDescription
7-0MPYR/W14h

Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are allowed for this design:

MPY: Frequency Multiplier

16 (0x10): 4

20 (0x14): 5

33 (0x21): 8.25

40 (0x28): 10

Note: This register should only be changed when JESD_EN=0.

7.5.3.20 RATE Register (Offset = 010Ah) [reset = 00h]

RATE is shown in Figure 7-81 and described in Table 7-66.

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JESD204C Receive Rate

Figure 7-81 RATE Register
76543210
RESERVEDRATE
R/W-00hR/W-00b
Table 7-66 RATE Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W00h
1-0RATER/W00b

Controls the frequency multiplier from the PHY PLL to the serial line rate. See PLL Control. Affects all lanes.

RATE: Multiplier

00b: 4

01b: 2

10b: 1

11b: 0.5

Note: This register should only be changed when JESD_EN=0.

7.5.3.21 LB_VRANGE Register (Offset = 010Bh) [reset = 00h]

LB_VRANGE is shown in Figure 7-82 and described in Table 7-67.

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JESD204C PLL VCO Range. Note: This register should only be changed when JESD_EN=0.

Figure 7-82 LB_VRANGE Register
76543210
RESERVEDVRANGE
R/W-0hR/W-0b
Table 7-67 LB_VRANGE Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0VRANGER/W0b

This bit must be set if the PLL/VCO frequency is below 2.17GHz. See PLL Control.

7.5.3.22 JSYNC_N Register (Offset = 0120h) [reset = 01h]

JSYNC_N is shown in Figure 7-67 and described in Table 7-52.

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JESD204C Manual Sync Request

Figure 7-83 JSYNC_N Register
76543210
RESERVEDJSYNC_N
R/W-00hR/W1C
Table 7-68 JSYNC_N Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0JSYNC_NR/W1b

Set this bit to 0 to manually assert the SYNC signal. For normal operation, leave this bit set to 1.

Note: Behavior of JSYNC_N=0 is undefined when JENC=1.

7.5.3.23 JTEST Register (Offset = 0121h) [reset = 00h]

JTEST is shown in Figure 7-84 and described in Table 7-69.

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JESD204C Test Control

Figure 7-84 JTEST Register
76543210
RESERVEDJTEST
R/W-000bR/W-00h
Table 7-69 JTEST Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4-0JTESTR/W0b

PRBS Test Modes:

0 : Test mode disabled. Normal operation (default)

1 : PRBS7 test mode

2 : PRBS9 test mode

3 : PRBS15 test mode

4 : PRBS31 test mode

5-31: RESERVED

When a PRBS test mode is enabled, see BER_EN.

Note: This register should only be changed when JESD_EN=0.

7.5.3.24 JTIMER Register (Offset = 0124h) [reset = 00h]

JTIMER is shown in Figure 7-85 and described in Table 7-70.

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Note: This register should only be changed when JESD_EN=0.

JESD204C Watchdog Timer

Figure 7-85 JTIMER Register
76543210
JTPLLRESERVEDJTRRESERVEDJTT
R/W-0bR/W-0bR/W-0bR/W-0bR/W-000b
Table 7-70 JTIMER Register Field Descriptions
BitFieldTypeResetDescription
7JTPLLR/W1b

When this bit is set, the SerDes PLL is also reset when the watchdog timer expires. When this bit is 0, only the SerDes receiver is reset.

6RESERVEDR/W0b
5-4JTRR/W00b

This register determines how much the watchdog counter is decremented when the link is up and CRC_FAULT is not set.

JTR : Watchdog Counter Decrement : Approximate Link Uptime % required to prevent the SerDes from being reset

0 : 1 : 99.25%

1 : 2 : 98.46%

2 : 8 : 94.12%

3 : 16 : 88.89%

3RESERVEDR/W0b
2-0JTTR/W0b

JESD204C watchdog counter threshold. When the watchdog counter reaches the threshold defined by JTT, the PHY layer is reset (including the PHY PLL(s) if JTPLL=1) and the watchdog timer is reset. Larger values of JTT cause the watchdog timer to take longer to intervene.

JTT : Watchdog Counter Threshold : Counter Duration [assuming FCLK = 10.24 GHz

0 : <Watchdog Timer Disabled> : <disabled>

1 : 217 : 102.4 μs

2 : 219 : 409.6 μs

3 : 232 : 1.63 ms

4 : 223 : 6.55 ms

5-7 : RESERVED : RESERVED

Note: The watchdog may not detect link up events shorter than 210 (1024) CLK cycles.

7.5.3.25 SYNC_EPW Register (Offset = 0127h) [reset = 00h]

SYNC_EPW is shown in Figure 7-86 and described in Table 7-71.

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JESD204C SYNC Error Report Pulse Width

Figure 7-86 SYNC_EPW Register
76543210
RESERVEDSYNC_EPW
R/W-00hR/W-000b
Table 7-71 SYNC_EPW Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00h
2-0SYNC_EPWR/W000b

Specifies the pulse width of SYNC that is used for reporting errors to the transmitter. When an error is detected that does not require link resynchronization, SYNC is asserted for SYNC_EPW link clock cycles (equal to 4*SYNC_EPW character durations). To disable error reporting over SYNC, set SYNC_EPW=0. The legal range for SYNC_EPW is 0 to 7.

Note: This register should only be changed when JESD_EN= 0.

7.5.3.26 CRC_TH Register (Offset = 0128h) [reset = 00h]

CRC_TH is shown in Figure 7-87 and described in Table 7-72.

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JESD204C CRC Error Thresholds

Figure 7-87 CRC_TH Register
76543210
RESERVEDCRC_ERR_RECCFC_ERR_TH
R/W-0hR/W-00bR/W-00b
Table 7-72 CRC_TH Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-2CRC_ERR_RECR/W0b

Specify how many contiguous, error-free multiblocks must be received to reset the CRC error counter (and un-trigger the CRC alarm if triggered).

0 : 1 multiblock

1 : 4 multiblocks

2 : 16 multiblocks

3 : 64 multiblocks

1-0CRC_ERR_THR/W0b

Specify how many multi-blocks must have CRC errors to trigger the CRC alarm. The receiver counts each error, but if a run of error-free multi-blocks occurs (as specified by CRC_ERR_REC), the error counter resets.

0 : 1 multiblock

1 : 2 multiblocks

2 : 4 multiblocks

3 : 8 multiblocks

Note: For each lane, the internal signal, CRC_FAULT, is set if the number of multi-blocks with CRC errors exceeds the threshold set by CRC_ERR_TH without a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC. CRC_FAULT is cleared when a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC is detected.

Note: This register should only be changed when JESD_EN=0.

7.5.3.27 LANE_ARSTAT Register (Offset = 012Ch) [reset = NA]

LANE_ARSTAT is shown in Figure 7-88 and described in Table 7-73.

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Lane Arrival Status

Figure 7-88 LANE_ARSTAT Register
76543210
RESERVEDLANE_ARR_RDY
R/W-00hR
Table 7-73 LANE_ARSTAT Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0LANE_ARR_RDYRNA

This bit is set when lane arrival times are captured and available for read in LANE_ARR. Lane arrival data is captured when all lanes are ready and the chip attempts to release the elastic buffer. This bit is cleared when JESD_EN=0 or JESD_RST=1.

7.5.3.28 LANE_INV Register (Offset = 012Eh) [reset = 0000h]

LANE_INV is shown in Figure 7-89 and described in Table 7-74.

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SerDes Lane Inversion

Figure 7-89 LANE_INV Register
15141312111098
LANE_INV[15:8]
R/W-00h
76543210
LANE_INV[7:0]
R/W-00h
Table 7-74 LANE_INV Register Field Descriptions
BitFieldTypeResetDescription
15-0LANE_INVR/W0000h Program LANE_INV[n]=1 to invert the bitstream through physical lane n. Use this if the differential pair is swapped between the transmitter and receiver.

7.5.3.29 LANE_SEL[15:0] Register (Offset = 0130h) [reset for LANE_SEL[n]=n]

LANE_SEL[15:0] forms a crossbar switch, and is a set of 16 registers for specifying which physical lane is bound to logical lane n. LANE_SEL[15:0] is shown in Figure 7-90 and described in Table 7-75.

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SerDes Lane Select for Logical Lane n (n = 0 - 15). LANE_SEL[0] is at the lowest address.

Figure 7-90 LANE_SEL[15:0] Register
76543210
RESERVEDLANE_SEL[n]
R/W-0hR/W-n
Table 7-75 LANE_SEL[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0LANE_SEL[n]R/Wn

Specify which physical lane (0 to 15) is bound to logical lane n. To bind physical lane p to logical lane n, program LANE_SEL[n]=p. For example, to bind logical lane 0 to physical lane 3, program LANE_SEL[0]=3.

Note: This register should only be changed when JESD_EN=0.

7.5.3.30 LANE_ARR[15:0] Register (Offset = 0140h) [Read only, reset = NA]

LANE_ARR[15:0] is a set of 16 registers for measuring the arrival time of lane n. LANE_ARR[15:0] is shown in Figure 7-91 and described in Table 7-76.

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SerDes Lane n Arrival Time (n = 0 - 15). LANE_ARR[0] is at the lowest address.

Figure 7-91 LANE_ARR[15:0] Register
76543210
RESERVEDLANE_ARR[n]
R-00bR
Table 7-76 LANE_ARR[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0h
5-0LANE_ARR[n]RNA

Returns the arrival time of lane n with respect to the internal LMFC/LEMC that is established by SYSREF. The value returned can be between 0 and 63 (inclusive), regardless of the multiframe/EMB length. These registers are valid only when LANE_ARR_RDY =1. See Programming RBD.

Note: The lane arrival data is captured when attempting to release the elastic buffer and LANE_ARR_RDY=0. All values are from the same release attempt.

Note: It may be necessary to use JESD_RST when starting the link to get accurate lane arrival values.

7.5.3.31 LANE_STATUS[15:0] Register (Offset = 0150h) [Read only, reset = NA]

LANE_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 7-92 and described in Table 7-77.

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SerDes Lane n Status (n = 0 - 15). LANE_STATUS[0] is at the lowest address.

Figure 7-92 LANE_STATUS[15:0] Register
76543210
RESERVEDLANE_STATUS[n]
R-00hR
Table 7-77 LANE_STATUS[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR00h
2F_EMB_SYNC[n]RNA

Returns 1 if logical lane n has frame or EMB synchronization.

1CG_BK_SYNC[n]RNA

Returns 1 if logical lane n has code-group or block synchronization.

0SIG_DET[n]RNA

Returns 1 if logical lane n is detecting a data signal (using loss-of-signal detector in PHY).

7.5.3.32 LANE_ERR[15:0] Register (Offset = 0160h) [reset = 00h]

LANE_ERR[15:0] is a set of 16 registers reporting errors for lane n. LANE_ERR[15:0] is shown in Figure 7-93 and described in Table 7-78.

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SerDes Lane n Error Flags (n = 0 - 15). LANE_ERR[0] is at the lowest address.

Figure 7-93 LANE_ERR[15:0] Register
76543210
LANE_ERR[n]
R/W1C
Table 7-78 LANE_ERR[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-0LANE_ERR[n]R/W1C00h

Sticky bits indicating various errors on lane n. A bit is set to indicate an error. Write a 1 to clear a bit.

[7] Alignment character found at unexpected location (8b/10b) or (extended)-multi-block pilot signal not in expected location (64b/66b)

[6] Multi-frame, multi-block, or extended-multi-block alignment lost.

[5] Frame alignment was lost (8b/10b only) or CRC_FAULT=1 (64b/66b).

[4] Code-group or block synchronization was lost.

[3] RESERVED

[2] Not-in-table or unexpected control character (8b/10b) or CRC (64b/66b) error occurred.

[1] Disparity error (8b/10b) or invalid sync header (64b/66b) occurred.

[0] Gearbox FIFO overflowed or underflowed. As long as the write clock frequency is correct the gearbox write clock can drift at least 3UI after this flag without causing data corruption.

Note: Lane Error Flags for extra or disabled lanes are undefined.

Note: LANE_ERR[6:1] are only detected for 8b/10b operation while sync_n=1

7.5.3.33 FIFO_STATUS[15:0] Register (Offset = 0170h) [Read only, reset = NA]

FIFO_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 7-94 and described in Table 7-79.

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SerDes Lane n Status (n = 0 - 15). FIFO_STATUS[0] is at the lowest address.

Figure 7-94 FIFO_STATUS[15:0] Register
76543210
RESERVEDPDIFF[n]
R-000bR
Table 7-79 FIFO_STATUS[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR000b
4-0PDIFF[n]RNA

This register returns the difference between the write and read pointers inside the gearbox FIFO for logical lane n.

For 8b/10b, values from 0-14 will be returned. For 64b/66b, values from 0-16 will be returned.

The values at the ends of the range (0 & 14 for 8b/10b or 0 & 16 for 64b/66b) indicate error positions that will cause the Gearbox FIFO overflow/underflow flag to be set in LANE_ERR. In both cases, 1 indicates minimum setup and the max value minus 1 indicates minimum hold.

Values are measured in the read clock. The tread size is approximately ½ of the effective link layer clock period (0.5/(LCR*FDR)). In terms of UI:

  • In 8b/10b mode, the nominal tread size is 20UI. The nominal tread size for the final tread (14) is 380UI±20UI.

  • In 64b/66b mode, the nominal tread size is 16.5UI. The nominal tread size for the final tread (16) is 412.5UI±16.5UI.

The PDIFF[n] value for disabled lanes and lanes enabled by EXTRA_LANE are undefined.

7.5.3.34 BER_EN Register (Offset = 01A0h) [reset = 00h]

BER_EN is shown in Figure 7-95 and described in Table 7-80.

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BER Measurement Control

Figure 7-95 BER_EN Register
76543210
RESERVEDBER_EN
R/W-0bR/W-0b
Table 7-80 BER_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0BER_ENR/W0bBER (bit-error-rate) test enable. After setting up the receiver parameters, the user can program JTEST to a PRBS mode, set JESD_EN, and then set BER_EN to enable the BER counters (see BER_CNTn). To clear and restart the counters, program BER_EN to 0 and then back to 1. The BER logic will self-synchronize to the incoming PRBS data after the rising edge of BER_EN.

7.5.3.35 BER_CNT Register (Offset = 01B0h) [reset = NA, read rnly]

BER_CNT is shown in Figure 7-96 and described in Table 7-81.

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BER Error Count for Lane n. Lane 0 is a the lowest address

Figure 7-96 BER_CNT Register
76543210
BER_CNT[n]
R/W-0b
Table 7-81 BER_CNT Register Field Descriptions
BitFieldTypeResetDescription
7-0BER_CNT[n]R/W0h

Returns the number of bit errors detected on lane n. This value will saturate at 255. The BER for lane n can be computed as follows:

BER = BER_CNT[n] / FBIT / TBER

Where TBER is the number of seconds that has elapsed from when BER_EN was set to when BER_CNT[n] was read. TBER is measured by the host system or clock.

Example: If BER_CNT[n] returns 2, and FBIT is 12.8Gbps, and TBER is 3600 seconds, the bit-error-rate is 2/12.8e9/3600 = 43e-15

Note: The error counters on disabled lanes and lanes enabled by EXTRA_LANE are undefined.

7.5.3.36 JPHY_CTRL Register (Offset = 01C1h) [reset = 43h]

JPHY_CTRL is shown in Figure 7-97 and described in Table 7-82.

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JESD204C SerDes Control. Note: This register should only be changed when JESD_EN = 0.

Figure 7-97 JPHY_CTRL Register
76543210
RESERVEDCDRRESERVEDOC_ENLOS_EN
R/W-0bR/W-100bR/W-0bR/W-1bR/W-1b
Table 7-82 JPHY_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0b
6-4CDRR/W100b

Control CDR (clock-data-recovery) setting. The default value should be appropriate, but other settings can be used to adjust the tracking rate or reduce CDR power consumption. The 2nd order modes are for tracking a frequency offset when the Tx and Rx do not share a common reference clock. This is not applicable to JESD204C. See CDR Settings.

3-2RESERVEDR/W00b
1OC_ENR/W1bEnable offset compensation/calibration for all lanes.
0LOS_ENR/W1bEnable loss-of-signal detector for all lanes.
Table 7-83 CDR Settings
CDRVote ThresholdTracking Rate [ppm]OrderSettling Time [UI]Activity %
0153132nd3683
176072nd3670
237232nd3650
318682nd3625
4 (default)15961st3683
532891st3650
614341st3625
77131st15245

7.5.3.37 EQ_CTRL Register (Offset = 01C2h) [reset = 00h]

EQ_CTRL is shown in Figure 7-98 and described in Table 7-84.

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SerDes Equalizer Control

Figure 7-98 EQ_CTRL Register
76543210
RESERVEDEQ_OVREQZ_OVREQHLDEQMODE
R/W-000bR/W-0bR/W-0bR/W-0bR/W-00b
Table 7-84 EQ_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000b
4EQ_OVRR/W0bWhen EQMODE=1, you can program EQ_OVR=1 to over-ride the equalizer level using the EQLEVEL[n] registers. Affects all lanes.
3EQZ_OVRR/W0bSet this bit to enable the EQZERO register (to override the equalizer’s zero frequency). When EQZ_OVR=0, the frequency is set based on the RATE register. Affects all lanes.
2EQHLDR/W0bWhen the equalizer is in fully-adaptive mode (EQMODE=1 and EQ_OVR=0), programming EQHLD will freeze (hold) the adaptation loop (for all lanes).
1-0EQMODER/W00b

Sets the equalizer mode (for all lanes): See Equalizer.

0: Equalizer disabled. Flat response with maximum gain.

1: Equalizer enabled. The equalizer is fully adaptive if EQ_OVR=0.

2: Precursor equalization analysis.

3: Postcursor equalization analysis.

7.5.3.38 EQZERO Register (Offset = 01C3h) [reset = 00h]

EQZERO is shown in Figure 7-99 and described in Table 7-85.

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SerDes Equalizer Zero.

Figure 7-99 EQZERO Register
76543210
RESERVEDEQZERO
R/W-000bR/W-00h
Table 7-85 EQZERO Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000b
4-0EQZEROR/W00hWhen EQZ_OVR=1, this field over-rides the equalizer’s zero frequency (for all lanes). When EQZ_OVR=0, the zero frequency is set automatically based on the RATE setting.

0x1F: 365 MHz (default setting for full and half-rate, RATE = 0 or 1)

0x1E: 275 MHz

0x1D: 195 MHz

0x1B: 140 MHz (default setting for quarter-rate mode, RATE = 2)

0x19: 105 MHz

0x10: 75 MHz

0x08: 55 MHz (default setting for eighth-rate, RATE = 3)

0x00: 50 MHz

7.5.3.39 LANE_EQ[15:0] Register (Offset = 01D0h) [reset = 08h]

LANE_EQ[15:0] is shown in Figure 7-100 and described in Table 7-86.

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SerDes Equalizer Level for Physical Lane [n]. LANE_EQ[0] is at the lowest address.

Figure 7-100 LANE_EQ[15:0] Register
76543210
RESERVEDEQBOOST[n]EQLEVEL[n]
R/W-0bR/W-00bR/W-00h
Table 7-86 LANE_EQ[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0b
6-5EQBOOST[n]R/W00b

Controls EQ boost for physical lane n.

EQBOOST : GAIN Boost : BW Change : Power Increase

0 : 0dB : 0% : 0mW

1 : 2dB : -30% : 0mW

2 : 4dB : +10% : 5mW

3 : 6dB : -20% : 5mW

4-0EQLEVEL[n]R/W00h

When EQ_OVR=1, this field controls the equalization level for lane n. The valid range is from 0 (least equalization) to 16 (most equalization).

7.5.3.40 LANE_EQS[15:0] Register (Offset = 01E0h) [reset = NA, read only]

LANE_EQS[15:0] is shown in Figure 7-101 and described in Table 7-87.

Return to the Register Summary Table.

Serdes Equalizer Status for Physical Lane n

Figure 7-101 LANE_EQS[15:0] Register
76543210
RESERVEDEQOVER[n]EQUNDER[n]EQLEVEL_S[n]
RRRR
Table 7-87 LANE_EQS[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR
6EQOVER[n]REQOVER status for PHY lane n pre/post cursor analysis. See Pre/Post Cursor Analysis Procedure.
5EQUNDER[n]REQUNDER status for PHY lane n pre/post cursor analysis. See Pre/Post Cursor Analysis Procedure..
4EQLEVEL_S[n]RThis field returns the equalizer level currently in effect for lane n. This is the count of the number of bits set in the thermometer encoded value from the stsrx EQLEVEL_S field for lane n.

7.5.3.41 ESRUN Register (Offset = 01F0h) [reset = 00h]

ESRUN is shown in Figure 7-102 and described in Table 7-88.

Return to the Register Summary Table.

Eye-Scan Run Control

Figure 7-102 ESRUN Register
76543210
RESERVEDESRUN
R/W-00hR/W-0b
Table 7-88 ESRUN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0ESRUNR/W0bAfter setting up eye-scan, set ESRUN=1 to run the eye-scan test. See Eye Scan Procedure.

7.5.3.42 ES_CTRL Register (Offset = 01F1h) [reset = 00h]

ES_CTRL is shown in Figure 7-103 and described in Table 7-89.

Return to the Register Summary Table. Note: Only change this register while ESRUN=0.

Eye-Scan Control

Figure 7-103 ES_CTRL Register
76543210
RESERVEDESLENES
R/W-00bR/W-00bR/W-0h
Table 7-89 ES_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-6ES_CTRLR/W00b
5-4ESLENR/W00b

Specify the length of the eye-scan test. Larger values will give more consistent results, but will take longer.

ESLEN : Number of Samples Analyzed

0 : 127

1 : 1032

2 : 8191

3 : 65535

Note: Many eye-scan modes only analyze zeros (or ones). Since they don’t analyze every sample, those modes will take longer to complete compared to a mode that analyzes all samples.

3-0ESR/W0h

Specify the eye-scan mode. Applies to all lanes.

ES : Eye-Scan Mode

0 : Eye-scan disabled (default)

1 : Compare. Counts mismatches between the normal sampler and the eye-scan sampler. Analyzes zeros and ones.

2 : Compare zeros. Same as ES=1, but only analyzes zeros.

3 : Compare ones. Same as ES=1, but only analyzes ones.

4 : Count ones. Increments ECOUNTn when the eye-scan sample is 1.

5-7 : RESERVED

8 : Average zero. Adjusts ESVO_Sn to the average voltage for a zero.

9 : Outer zero. Adjusts ESVO_Sn to the lowest voltage for a zero.

10 : Inner zero. Adjusts ESVO_Sn to the highest voltage for a zero.

11 : RESERVED

12 : Average one. Adjusts ESVO_Sn to the average voltage for a one.

13 : Outer one. Adjusts ESVO_Sn to the highest voltage for a one.

14 : Inner one. Adjusts ESVO_Sn to the lowest voltage for a one.

15 : RESERVED

7.5.3.43 ESPO Register (Offset = 01F2h) [reset = 00h]

ESPO is shown in Figure 7-104 and described in Table 7-90.

Return to the Register Summary Table.

Eye-Scan Phase Offset

Figure 7-104 ESPO Register
76543210
RESERVEDESPO
R/W-0bR/W-00h
Table 7-90 ESPO Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6-0ESPOR/W0b

Eye-scan phase offset for all lanes. This adjusts the sampling instant of the eye-scan sampler compared to the normal sampler. This is a signed value from -64 to +63 and the step size is 1/32th of a UI.

Note: Only change this register while ESRUN=0.

7.5.3.44 ESVO Register (Offset = 01F3h) [reset = 00h]

ESVO is shown in Figure 7-105 and described in Table 7-91.

Return to the Register Summary Table.

Eye-Scan Voltage Offset

Figure 7-105 ESVO Register
76543210
RESERVEDESVO
R/W-00bR/W-00h
Table 7-91 ESVO Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5-0ESVOR/W00h

Eye-scan voltage offset for all lanes. This adjusts the voltage threshold of the eye-scan sampler. This is a signed value from -32 to +31. The step size is about 10mV (giving an adjustment range of about -320mV to +310mV). This field is ignored for eye-scan modes that adjust the voltage offset automatically and return a result on ESVO_S[n].

Note: This register should only be changed when ESRUN=0.

7.5.3.45 ES_BIT_SELECT Register (Offset = 01F4h) [reset = 00h]

ES_BIT_SELECT is shown in Figure 7-106 and described in Table 7-92.

Return to the Register Summary Table.

Eye-Scan Bit Select.

Figure 7-106 ES_BIT_SELECT Register
76543210
RESERVEDES_BIT_SELECT
R/W-000bR/W-00h
Table 7-92 ES_BIT_SELECT Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000b
4-0ES_BIT_SELECTR/W00h

Eye-scan only runs on every 20th bit. This field specifies which bit position the eye-scan runs on (valid range is 0 to 19). Eye-scans may be run with all possible values of ES_BIT_SELECT and the results combined. Alternatively, results can be kept separate to see the effects of any duty cycle distortion / repetitive jitter.

Note: This register should only be changed when ESRUN=0.

7.5.3.46 ECOUNT_CLR Register (Offset = 01F5h) [reset = 00h]

ECOUNT_CLR is shown in Figure 7-107 and described in Table 7-93.

Return to the Register Summary Table.

SerDes Error Counter Clear

Figure 7-107 ECOUNT_CLR Register
76543210
RESERVEDECOUNT_CLR
R/W-00hR/W-0b
Table 7-93 ECOUNT_CLR Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0ECOUNT_CLRR/W0bProgram this to a 1 and then to 0 to clear the ECOUNT counters

7.5.3.47 ESDONE Register (Offset = 01F6h) [reset = NA, read-only]

ESDONE is shown in Figure 7-108 and described in Table 7-94.

Return to the Register Summary Table.

Eye-Scan Process Done

Figure 7-108 ESDONE Register
76543210
ESDONE[15:8]
R
ESDONE[7:0]
R
Table 7-94 ESDONE Register Field Descriptions
BitFieldTypeResetDescription
15-0ESDONE[15:0]RNAESDONE[n] returns a 1 to indicate that the eye-scan procedure is completed on physical lane n. You must make sure that ESDONE[n] returns 1 before reading ESVO_S[n] or ECOUNT[n].

7.5.3.48 ESVO_S[15:0] Register (Offset = 0200h) [reset = NA, read-only]

ESVO_S[15:0] is shown in Figure 7-109 and described in Table 7-95.

Return to the Register Summary Table.

Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESVO_S[0] is at the lowest address.

Figure 7-109 ESVO_S[15:0] Register
76543210
RESERVEDESVO_S[n]
RR
Table 7-95 ESVO_S[15:0] Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDRNA
5-0ESVO_S[n]RNAReturns the voltage offset result from the eye-scan on physical lane n. Applies to eye-scan modes that compute the voltage offset automatically. Only valid when ESDONE[n] returns 1.

7.5.3.49 ESCOUNT[15:0] Register (Offset = 0210h) [reset = NA, read-only]

ESCOUNT[15:0] is shown in Figure 7-110 and described in Table 7-96.

Return to the Register Summary Table.

Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESCOUNT[0] is at the lowest address.

Figure 7-110 ESCOUNT[15:0] Register
76543210
ESCOUNT[15:8][n]
R
ESCOUNT[7:0][n]
R
Table 7-96 ESCOUNT[15:0] Register Field Descriptions
BitFieldTypeResetDescription
15-0ESCOUNT[n]RNAReturns the mismatch count for physical lane n (applies to eye-scan modes that count mismatches). Only valid when ESDONE[n] returns 1.

7.5.3.50 LOS_TH Register (Offset = 0234h) [reset = 08h]

LOS_TH is shown in Figure 7-111 and described in Table 7-97.

Return to the Register Summary Table.

SerDes Loss-of-signal Theshold

Figure 7-111 LOS_TH Register
76543210
RESERVEDLOS_TH
R/W-0hR/W-0h
Table 7-97 LOS_TH Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0LOS_THR/W0h

Specifies the threshold for the loss-of-signal detector. Applies when LOS_EN=1. Affects all lanes.

LOS_TH : Approximate Threshold (mV)

0, 1 : RESERVED

2 - 15 : 15*(LOS_TH)

7.5.3.51 EQCNTSZ Register (Offset = 0235h) [reset = 00h]

EQCNTSZ is shown in Figure 7-112 and described in Table 7-98.

Return to the Register Summary Table.

SerDes Equalizer Counter Size

Figure 7-112 EQCNTSZ Register
76543210
R/W-0hR/W-0h
Table 7-98 EQCNTSZ Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0EQCNTSZR/W0h

Equalizer counter size: Adjusts how many votes must be accumulated to cause the adaptive equalizer gain to change. Affects all lanes. This is for debug purposes only and the user should generally not need to change this setting.

EQCNTSZ : Equalizer Vote Counter Size (votes required to adjust gain)

0 : (default) 511

1 : RESERVED

2 : 1

3 : 3

4 : 7

5 : 15

6 : 31

7 : 63

8 : 127

9 : 255

10-15 : RESERVED

7.5.3.52 CDRLOCK Register (Offset = 0238h) [reset = 00h]

CDRLOCK is shown in Figure 7-113 and described in Table 7-99.

Return to the Register Summary Table.

SerDes CDR Lock/Freeze.

Figure 7-113 CDRLOCK Register
76543210
RESERVEDCDRLOCK
R/W-00hR/W-0b
Table 7-99 CDRLOCK Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0CDRLOCKR/W0bWhen set, the CDR is frozen and no longer tracks. When the CDR is operating in first-order mode, set CDRLOCK to freeze the CDRPHASE value to inspect it.

7.5.3.53 CDRPHASE Register (Offset = 0239h) [reset = NA, read-only]

CDRPHASE is shown in Figure 7-114 and described in Table 7-100.

Return to the Register Summary Table.

SerDes CDR Phase Status

Figure 7-114 CDRPHASE Register
76543210
CDRPHASE
R
Table 7-100 CDRPHASE Register Field Descriptions
BitFieldTypeResetDescription
7-0CDRPHASERReturns the current CDR phase value for the lane specified by RXDLANE. It is recommended to set CDRLOCK=1 before reading this register. The format is gray-coded. Refer to CDRPHASE Status for the coding.

7.5.3.54 PLL_STATUS Register (Offset = 0250h) [reset = NA, read only]

PLL_STATUS is shown in Figure 7-67 and described in Table 7-52.

Return to the Register Summary Table.

SerDes PLL Status

Figure 7-115 PLL_STATUS Register
76543210
PLL_LOCK_STSPLL_LOCK_LOST
R-0hR/W1C-0h
Table 7-101 PLL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-4PLL_LOCK_STSR0hThis field returns the LOCK signal from all four SerDes macros (3:0). This field can be used for functional (fault) testing of the PLL lock detectors.
3-0PLL_LOCK_LOSTR/W1C0hPLL_LOCK_LOST[n] is set whenever the LOCK signal from a SerDes PLL is low.

bit 0: lanes 0 - 3

bit 1: lanes 4 - 7

bit 2: lanes 8 - 11

bit 3: lanes 12 - 15

This bit is sticky (remains set even if the PLL acquires lock). Write 1 to clear a bit. These bits are for debug purposes and allow the SPI to monitor if any SerDes PLL loses lock even briefly.

7.5.3.55 JESD_RST Register (Offset = 0253h) [reset = 0x00]

JESD_RST is shown in Figure 7-116 and described in Table 7-102.

Return to the Register Summary Table.

JESD Reset

Figure 7-116 JESD_RST Register
7654321
RESERVEDJESD_RST
R/W-00hR/W-0h
Table 7-102 JESD_RST Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00hRESERVED
0JESD_RSTR/W0bWhen set, this bit holds the digital portion of the JESD circuitry in reset but does not affect the physical lane. It may be necessary to set this bit prior to setting JESD_EN = 1 and then clear this bit at a later time to start processing the JESD data. This allows the supply to settle from the large change in power that occurs when starting the PHY and JESD clocks. This is especially important if the user plans to use the LANE_ARR values, since these values are captured only the first time the elastic buffer attempts to release.

7.5.3.56 EXTREF_EN Register (Offset = 02B0h) [reset = 00h]

EXTREF_EN is shown in Figure 7-117 and described in Table 7-103.

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Enable External Reference

Figure 7-117 EXTREF_EN Register
76543210
RESERVEDEXTREF_EN
R/W-00hR/W-0b
Table 7-103 EXTREF_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0EXTREF_ENR/W0bSetting this bit enable the use of an external reference voltage on the EXTREF ball.

CUR_2X_EN Register (Offset = 02B1h) [reset = 00h]

CUR_2X_EN is shown in Figure 7-118 and described in Table 7-104.

Return to the Register Summary Table.

DAC Current Doubler Enable

Figure 7-118 CUR_2X_EN Register
76543210
RESERVEDCUR_2X_EN
R/W-00hR/W-0b
Table 7-104 CUR_2X_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0CUR_2X_ENR/W0bSetting this bit doubles the DAC output current.

7.5.3.57 DAC_OFS_CHG_BLK Register (Offset = 02CFh) [reset = 00h]

DAC_OFS_CHG_BLK is shown in Figure 7-119 and described in Table 7-105.

Return to the Register Summary Table.

DAC Offset Adjustment Change Block

Figure 7-119 DAC_OFS_CHG_BLK Register
76543210
RESERVEDDAC_OFS_CHG_BLK
R/W-00hR/W-0b
Table 7-105 DAC_OFS_CHG_BLK Register Field Descriptions
BitFieldTypeResetDescription
7-1R/W00h
0DAC_OFS_CHG_BLKR/W0bWhen set, changes to DAC_OFS[n] are not propagated to the high-speed clocks and both DACs continue to use their current value. When this is changed from 1 to 0 the new DAC_OFS[n] values will be applied to both DACs in the same clock cycle.

7.5.3.58 DP_EN Register (Offset = 02E0h) [reset = 00h]

DP_EN is shown in Figure 7-120 and described in Table 7-106.

Return to the Register Summary Table.

Datapath Enable.

Figure 7-120 DP_EN Register
76543210
RESERVEDDP_EN
R/W-00hR/W-0b
Table 7-106 DP_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0DP_ENR/W0b

Setting this bit enables datapath operation. When cleared, the datapath is held in reset. This bit should be set after the chip is configured for proper operation.

Note: This register should only be changed from 0 to 1 when FUSE_DONE=1.

7.5.3.59 DUC_L Register (Offset = 02E1h) [reset = 00h]

DUC_L is shown in Figure 7-121 and described in Table 7-107.

Return to the Register Summary Table.

DUC Interpolation Factor.

Figure 7-121 DUC_L Register
76543210
RESERVEDDUC_L
R/W-0hR/W-0h
Table 7-107 DUC_L Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0DUC_LR/W0h

DUC Interpolation Factor

0: 1x

1: 2x

2: 3x

3: 4x

4: 6x

5: 8x

6: 12x

7: 16x

8: 24x

9: 32x

10: 48x

11: 64x

12: 96x

13: 128x

14: 192x

15: 256x

Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

7.5.3.60 DUC_GAIN Register (Offset = 02E2h) [reset = 00h]

DUC_GAIN is shown in Figure 7-122 and described in Table 7-108.

Return to the Register Summary Table.

Figure 7-122 DUC_GAIN Register
76543210
DUC_GAIN3DUC_GAIN2DUC_GAIN1DUC_GAIN0
R/W-00bR/W-00bR/W-00bR/W-00b
Table 7-108 DUC_GAIN Register Field Descriptions
BitFieldTypeResetDescription
7-6DUC_GAIN3R/W00b

DUC_GAINn adjusts the gain of DUCn (in the channel bonder)

0: 0dB

1: -6dB

2: -12dB

3: RESERVED

Note: When the DUCs are configured for complex output (DUC_FORMAT=1), DUC2 and DUC3 cannot be used. In that case, DUC_GAIN2 and DUC_GAIN3 adjust the gain of the imaginary outputs of DUC0 and DUC1 respectively.

Note: This register should only be changed when DP_EN=0.

5-4DUC_GAIN2R/W00b
3-2DUC_GAIN1R/W00b
1-0DUC_GAIN0R/W00b

7.5.3.61 DUC_FORMAT Register (Offset = 02E3h) [reset = 00h]

DUC_FORMAT is shown in Figure 7-123 and described in Table 7-109.

Return to the Register Summary Table.

DUC Output Format

Figure 7-123 DUC_FORMAT Register
76543210
RESERVEDDUC_FORMAT
R/W-00hR/W-0b
Table 7-109 DUC_FORMAT Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0DUC_FORMATR/W0b

0: DUC outputs are real (DUC mixer converts complex to real by discarding the imaginary part). Up to 4 DUCs can be enabled.

1: DUC outputs are complex. Up to 2 DUCs can be enabled (DUC0 and DUC1).

Note: This register should only be changed when DP_EN=0.

7.5.3.62 DAC_SRC Register (Offset = 02E4h) [reset = 00h]

DAC_SRC is shown in Figure 7-124 and described in Table 7-110.

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DAC Source

Figure 7-124 DAC_SRC Register
76543210
DAC_SRC1DAC_SRC0
R/W-0hR/W-0h
Table 7-110 DAC_SRC Register Field Descriptions
BitFieldTypeResetDescription
7-4DAC_SRC1R/W0h

When the DUCs are disabled (LT<=1), DAC_SRCn selects which input stream is sent to DACn. When the DUCs are enabled (LT>=2), DAC_SRCn controls which DUC outputs are routed (summed) to DACn (and the meaning of the bits depends on DUC_FORMAT).

Signals Routed to DACn when DAC_SRCn[m] is set:

LT=0.5 or 1 (DUCs disabled)

DAC_SRCn[0]: Input Stream 0 (I)

DAC_SRCn[1]: Input Stream 1 (Q)

DAC_SRCn[2]: n/a

DAC_SRCn[3]: n/a

LT is 2 or higher (DUCs enabled) Register Bit

DAC_SRCn[x] : DUC_FORMAT=0 (real) : DUC_FORMAT=1 (complex)

DAC_SRCn[0] : DUC0 (real) : DUC0 (real)

DAC_SRCn[1] : DUC1 (real) : DUC1 (real)

DAC_SRCn[2] : DUC2 (real) : DUC0 (imag)

DAC_SRCn[3] : DUC3 (real) : DUC1 (imag)

If more than one signal is routed to the same DAC, the signals are summed together. Use DUC_GAIN to avoid saturation in this case.

While it is possible to sum a real output with an imaginary output, no practical application requires that, so it is not tested or supported. When LT=0.5 or 1, no summing is supported. Only DAC_SRCn[0] or DAC_SRCn[1] should be set

Note: This register should only be changed when DP_EN=0.

3-0DAC_SRC0R/W0b

7.5.3.63 MXMODE Register (Offset = 02E8h) [reset = 00h]

MXMODE is shown in Figure 7-125 and described in Table 7-111.

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DAC Output Mode. Note: This register should only be changed when DP_EN=0.

Figure 7-125 MXMODE Register
76543210
RESERVEDMXMODE1RESERVEDMXMODE0
R/W-0bR/W-000bR/W-0bR/W-000b
Table 7-111 MXMODE Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0b
6-4MXMODE1R/W000b

Specify the DAC pulse format for DACB.

0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at n*FS)

1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2n*FS)

2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS)

3: DES2X – Samples provided by the DES interpolator (low-pass mode)

4: DES2XH – Samples provided by the DES interpolator (high-pass mode)

5: DES1X – Both samples are provided by the input stream

6: Disabled – DACA is disabled

7: RESERVED

Note: If either MXMODE1 or MXMODE0 is set to DES1X, the other must be set to either DES1X or Disabled. User must also set DUC_L=0.

3RESERVEDR/W0b
2-0MXMODE0R/W0b

Specify the DAC pulse format for DACA.

0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at n*FS)

1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2n*FS)

2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS)

3: DES2X – Samples provided by the DES interpolator (low-pass mode)

4: DES2XH – Samples provided by the DES interpolator (high-pass mode)

5: DES1X – Both samples are provided by the input stream

6: Disabled – DACA is disabled

7: RESERVED

Note: If either MXMODE1 or MXMODE0 is set to DES1X, the other must be set to either DES1X or Disabled. User must also set DUC_L=0.

7.5.3.64 TRUNC_HLSB Register (Offset = 02EAh) [reset = 00h]

TRUNC_HLSB is shown in Figure 7-126 and described in Table 7-112.

Return to the Register Summary Table.

Truncation Half LSB Offset

Figure 7-126 TRUNC_HLSB Register
76543210
RESERVEDTRUNC_HLSB
R/W-00hR/W-0b
Table 7-112 TRUNC_HLSB Register Field Descriptions
BitFieldTypeResetDescription
7-1R/W0h
0TRUNC_HLSBR/W0b

adds ½ LSB offset for < 16-bit resolution modes or devices. For a mode or device with < 16-bit output resolution, setting this bit adds a 1/2 LSB offset to reduce the average offset introduced by truncation.

Note: This register should only be changed when DP_EN=0

7.5.3.65 TX_EN_SEL Register (Offset = 02F8h) [reset = 03h]

TX_EN_SEL is shown in Figure 7-127 and described in Table 7-113.

Return to the Register Summary Table.

Transmitter Enable Control Selection.

Figure 7-127 TX_EN_SEL Register
76543210
RESERVEDQUIET_TX_DISABLEFAST_TX_ENUSE_TX_EN1USE_TX_EN0
R/W-0hR/W-0bR/W-0bR/W-1bR/W-1b
Table 7-113 TX_EN_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3QUIET_TX_DISABLER/W0b

0: Transmission is disabled after DEM and dither by sending a static aging safe code. For some configurations and frequencies, the outputs will have higher noise than a static mid-scale code would normally have. However, this mode has the lowest latency from transmit enable to DAC output.

1: When transmission is disabled, the input to DEM and dither is muted to minimize the output noise. This increases the latency from transmit enable to DAC output by 56 DAC clocks

Note: This bit may only be set when FAST_TX_EN=1.

2FAST_TX_ENR/W0b

0: When the transmit enables are both low, JESD and datapath clocks are shutdown to save power. When transmission is re-enabled the outputs remain muted until valid data is available at the output.

1: No power saving is performed and transmit enables can be used independently. Latency from transmit enable to DAC outputs is reduced in this mode.

1USE_TX_EN1R/W1b

0: DACB is controlled by the TXEN1 ball. In this mode, TX_EN1 register is ignored.

1: DACB is controlled by the TX_EN1 register. In this mode the TXEN1 ball input does not affect the transmit enable for DACB.

Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported).

0USE_TX_EN0R/W1b

0: DACA is controlled by the TXEN0 ball. In this mode, TX_EN0 register is ignored.

1: DACA is controlled by the TX_EN0 register. In this mode the TXEN0 ball input does not affect the transmit enable for DACA.

Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported).

7.5.3.66 TX_EN Register (Offset = 02F9h) [reset = 03h]

TX_EN is shown in Figure 7-128 and described in Table 7-114.

Return to the Register Summary Table.

Transmitter Enable Control

Figure 7-128 TX_EN Register
76543210
TX_EN1TX_EN0
R/W-00hR/W-1bR/W-1b
Table 7-114 TX_EN Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W00h
1TX_EN1R/W1bWhen USE_TX_EN1 = 1, this bit controls the transmit enable for DACB.

Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).

0TX_EN0R/W1bWhen USE_TX_EN0 = 1, this bit controls the transmit enable for DACA

Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).

7.5.3.67 NCO_CTRL Register (Offset = 0300h) [reset = 00h]

NCO_CTRL is shown in Figure 7-129 and described in Table 7-115.

Return to the Register Summary Table. Note: This register should only be changed when DP_EN=0.

NCO Enable

Figure 7-129 NCO_CTRL Register
76543210
FR_ENRESERVEDNCO_SCDDS_ENNCO_EN
R/W-0bR/W-0hR/W-0bR/W-0bR/W-0b
Table 7-115 NCO_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7FR_ENR/W0bWhen set, the Fast Reconfiguration (FR) interface is enabled and NCO frequency, phase, dither, and accumulator reset is controlled by the FR registers rather than the SPI registers.
6-3RESERVEDR/W0h
2NCO_SCR/W0bSelf-Coherent NCO Mode: When this bit is set, all NCOs use the reference counter from the NCO in DDS/DUC channel 0. This is typically used along with the NCO_SS register. This only impacts phase-coherent mode (NCO_CONT=0).
1DDS_ENR/W0bWhen set, all DUCs are configured for DDS operation once DP_EN is set. See DDS Operation in Section 7.4.1 for details.
0NCO_ENR/W0bWhen set, DUC samples are mixed with the NCO.

7.5.3.68 NCO_CONT Register (Offset = 0301h) [reset = 00h]

NCO_CONT is shown in Figure 7-130 and described in Table 7-116.

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NCO Phase Continuous Mode

Figure 7-130 NCO_CONT Register
76543210
RESERVEDNCO_CONT
R/W-0hR/W-0h
Table 7-116 NCO_CONT Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0NCO_CONTR/W0h

For each bit NCO_CONT[n], if set, NCOn operates in phase-continuous mode. This means that frequency changes occur without seeding the phase accumulator. If the bit is clear, NCOn operates in phase-coherent mode. During frequency changes, the phase accumulator is seeded from a main counter. This means that if changing from frequency A to B and then back to A, the phase returns to what it would have been if the change never occurred.

Note: This register should only be changed when DP_EN=0.

7.5.3.69 NCO_SYNC Register (Offset = 0302h) [reset = 00h]

NCO_SYNC is shown in Figure 7-131 and described in Table 7-117.

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NCO Synchronization Configuration

Figure 7-131 NCO_SYNC Register
76543210
RESERVEDNCO_SYNC_SRC
R/W-00hR/W-00b
Table 7-117 NCO_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W00h
1-0NCO_SYNC_SRCR/W00b

If FR_EN=0:

This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by NCO_AR and the application of changes to NCO_DITH_EN, FREQ, and PHASE.

0: Setting SPI_SYNC will immediately perform specified events. (All will occur in the same clock cycle.)

1: Setting SPI_SYNC will cause the specified events to occur on the next SYSREF rising edge.

2: While SPI_SYNC is high, the specified events will occur on every SYSREF rising edge.

3: While SPI_SYNC is high, the LSb of the “I” input to DUC0 will cause the specified events. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input.

If FR_EN=1:

This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by FR_NCO_AR and the application of changes to FR_NCO_DITH_EN, FR_FREQL, FR_FREQS, and FR_PHASE.

0: If FRS is set, the specified events is performed at the rising edge of FRCS. (All will occur in the same clock cycle.)

1: Reserved

2: RESERVED

3: If FRS is set, the LSb of the “I” input to DUC0 will cause the specified events following the rising edge of FRCS. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input. While waiting for the LSb trigger, zero will be used for the LSb data. The LSb will immediately return to being used as data after the 4th consecutive high sample.

Note: This register should only be changed when SPI_SYNC=0 and the FR interface is idle (FRCS=1).

7.5.3.70 NCO_AR Register (Offset = 0303h) [reset = 0Fh]

NCO_AR is shown in Figure 7-132 and described in Table 7-118.

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NCO Accumulator Reset

Figure 7-132 NCO_AR Register
76543210
RESERVEDNCO_AR
R/W-0hR/W-0h
Table 7-118 NCO_AR Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0NCO_ARR/W0h

For each bit NCO_AR[n], if set, the accumulator for NCOn will be reset on every sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=1.

7.5.3.71 SPI_SYNC Register (Offset = 0304h) [reset = 00h]

SPI_SYNC is shown in Figure 7-133 and described in Table 7-119.

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SPI Sync Bit

Figure 7-133 SPI_SYNC Register
76543210
RESERVEDSPI_SYNC
R/W-00hR/W-0b
Table 7-119 SPI_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0SPI_SYNCR/W0b

Writing ‘1’ to this register when it is ‘0’ will trigger synchronization events that are bound to this register (see NCO_SYNC_SRC). This register will return the last value written.

Note: Whether this register is edge or level sensitive depends on the setting for NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=1.

NCO_SS Register (Offset = 0305h) [reset = 00h]

NCO_SS is shown in Figure 7-134 and described in Table 7-120.

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NCO_SS Bit

Figure 7-134 NCO_SS Register
76543210
RESERVEDNCO_SS
R/W-00hR/W-0b
Table 7-120 NCO_SS Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0NCO_SSR/W0b

When this bit is set, all NCOs will continuously self-synchronize every 256 DAC clock cycles.

In a radiation environment, the user can set NCO_SS to continuously transfer the upset-immune AMP, FREQ and PHASE register values to the internal (non-immune) registers inside the NCOs. This is helpful for generating tones under radiation without the need for an external, periodic synchronization source (such as SYSREF).

NCO_SS can be changed while the NCOs are operating (DP_EN=1). To write a new FREQ, AMP, or PHASE value, clear NCO_SS first, and then set it again after the new values are written. All values go into effect simultaneously on all NCOs.

The user should make sure that NCO_AR=0 whenever NCO_SS=1 (otherwise the NCO accumulators and/or reference counters keep getting reset).

If the user also sets NCO_SC=1 and NCO_CONT=0, then all four NCOs maintain coherency with each other under radiation, but there may be no coherence with an external component. Each NCO accumulator is continuously seeded from the reference counter in DUC/DDS channel 0. This feature can be used to generate coherent harmonic tones to cancel out harmonic distortion in the DAC.

AMP[3:0] Register (Offset = 0318h) [reset = 0000h]

AMP[3:0] is described in Table 7-121. AMP[0] starts at address 0x0318, AMP[1] at address 0x031A, AMP[2] at address 0x031C and AMP[3] at address 0x031E.

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Table 7-121 AMP[3:0] Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP[3:0]R/W0000h

Specifies the DDS amplitude for DDS channel n. 16-bit signed value. This register only applies to DDS Operation.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

7.5.3.72 FREQ[0] Register (Offset = 0320h) [reset = 0000000000000000h]

FREQ[0] is described in Table 7-122.

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FREQ for NCO0 Accumulator.

Table 7-122 FREQ[0] Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[0]R/W

0000

0000

0000

0000h

The NCO frequency (FNCO) is:

FNCO = FREQ[0] * 2-64 * FCLK

where FCLK is the sample frequency of the DAC. FREQ[0] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[0] = 264 * FNCO /FCLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.73 FREQ[1] Register (Offset = 0328h) [reset = 0000000000000000h]

FREQ[1] is described in Table 7-123.

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FREQ for NCO1 Accumulator.

Table 7-123 FREQ[1] Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[1]R/W

0000

0000

0000

0000h

The NCO frequency (FNCO) is:

FNCO = FREQ[1] * 2-64 * FCLK

where FCLK is the sample frequency of the DAC. FREQ[1] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[1] = 264 * FNCO /FCLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.74 FREQ[2] Register (Offset = 0330h) [reset = 0000000000000000h]

FREQ[2] is described in Table 7-124.

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FREQ for NCO2 Accumulator.

Table 7-124 FREQ[2] Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[2]R/W

0000

0000

0000

0000h

The NCO frequency (FNCO) is:

FNCO = FREQ[2] * 2-64 * FCLK

where FCLK is the sample frequency of the DAC. FREQ[2] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[2] = 264 * FNCO /FCLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.75 FREQ[3] Register (Offset = 0338h) [reset = 0000000000000000h]

FREQ[3] is described in Table 7-125.

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FREQ for NCO3 Accumulator.

Table 7-125 FREQ[3] Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ[3]R/W

0000

0000

0000

0000h

The NCO frequency (FNCO) is:

FNCO = FREQ[3] * 2-64 * FCLK

where FCLK is the sample frequency of the DAC. FREQ[3] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[3] = 264 * FNCO /FCLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.76 PHASE0 Register (Offset = 0340h) [reset = 0000h]

PHASE0 is described in Table 7-126.

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Phase for NCO0 Accumulator.

Table 7-126 PHASE0 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE0R/W0h

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE0* 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.77 PHASE1 Register (Offset = 0342h) [reset = 0000h]

PHASE1 is described in Table 7-127.

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Phase for NCO1 Accumulator.

Table 7-127 PHASE1 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE1R/W0h

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE1 * 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.78 PHASE2 Register (Offset = 0344h) [reset = 0000h]

PHASE2 is described in Table 7-128.

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Phase for NCO2 Accumulator.

Table 7-128 PHASE2 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE2R/W0h

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE2 * 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.79 PHASE3 Register (Offset = 0346h) [reset = 0000h]

PHASE3 is described in Table 7-129.

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Phase for NCO3 Accumulator.

Table 7-129 PHASE3 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE3R/W0h

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE3 * 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

AMP_R[3:0] Register (Offset = 0378h) [reset = NA]

AMPR[3:0] is described in Table 7-130. AMP_R[0] starts at addess offset 0x0378, AMP_R[1] at address offset 0x37A, AMP_R[2] at address offset 0x37C and AMP_R[3] at address offset 0x37E

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Table 7-130 AMP_R[3:0] Register Field Descriptions
BitFieldTypeResetDescription
15-0AMP_R[n]RNAThis provides a readback of the amplitude setting that is currently in use by the DDS channel n. Format is 16-bit signed. This register is only applicable when DDS_EN=1. When DDS_EN=0, the return value is undefined. The value is sampled as each byte is read, so it may return incoherent data if the amplitude changes during readback.

7.5.3.80 FREQ_R0 Register (Offset = 0380h) [reset = NA, read-only]

FREQ_R0 is described in Table 7-131.

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Readback for Frequency for NCO0

Table 7-131 FREQ_R0 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R0RNAThis provides a readback of the FREQ setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.81 FREQ_R1 Register (Offset = 0388h) [reset = NA, read-only]

FREQ_R1 is described in Table 7-132.

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Readback for Frequency for NCO1

Table 7-132 FREQ_R1 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R1RNAThis provides a readback of the FREQ setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.82 FREQ_R2 Register (Offset = 0390h) [reset = NA, read-only]

FREQ_R2 is described in Table 7-133.

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Readback for Frequency for NCO2

Table 7-133 FREQ_R2 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R2RNAThis provides a readback of the FREQ setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.83 FREQ_R3 Register (Offset = 0398h) [reset = NA, read-only]

FREQ_R3 is described in Table 7-134.

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Readback for Frequency for NCO3

Table 7-134 FREQ_R3 Register Field Descriptions
BitFieldTypeResetDescription
63-0FREQ_R3RNAThis provides a readback of the FREQ setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.84 PHASE_R0 Register (Offset = 03A0h) [reset = NA, read-only]

PHASE_R0 is described in Table 7-135.

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Readback for Phase Word for NCO0

Table 7-135 PHASE_R0 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R0R/W0hThis provides a readback of the PHASE setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.85 PHASE_R1 Register (Offset = 03A2h) [reset = NA, read-only]

PHASE_R1 is described in Table 7-136.

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Readback for Phase Word for NCO1

Table 7-136 PHASE_R1 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R1R/WNAThis provides a readback of the PHASE setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.86 PHASE_R2 Register (Offset = 03A4h) [reset = NA, read-only]

PHASE_R2 is described in Table 7-137.

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Readback for Phase Word for NCO2

Table 7-137 PHASE_R2 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R2R/WNAThis provides a readback of the PHASE setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.87 PHASE_R3 Register (Offset = 03A6h) [reset = NA, read-only]

PHASE_R3 is described in Table 7-138.

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Readback for Phase Word for NCO3

Table 7-138 PHASE_R3 Register Field Descriptions
BitFieldTypeResetDescription
15-0PHASE_R3R/WNAThis provides a readback of the PHASE setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.88 FR_FRS_R Register (Offset = 03E0h) [reset = NA, read-only]

FR_FRS_R is shown in Figure 7-135 and described in Table 7-139.

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Readback for FR Syncrhonization

Figure 7-135 FR_FRS_R Register
76543210
FR_FRS_RRESERVED
RR
Table 7-139 FR_FRS_R Register Field Descriptions
BitFieldTypeResetDescription
7FR_FRS_RRNA

This provides readback for the value of FRS in the last transaction.

Note: This value is not synchronized and should only be read while the FR interface is static.

6-0RESERVEDRNA

7.5.3.89 FR_NCO_AR_R Register (Offset = 03E1h) [reset = NA, read-only]

FR_NCO_AR_R is shown in Figure 7-136 and described in Table 7-140.

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Readback for FR NCO Accumulator Reset

Figure 7-136 FR_NCO_AR_R Register
76543210
RESERVEDFR_NCO_AR_R
RR
Table 7-140 FR_NCO_AR_R Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRNA
3-0FR_NCO_AR_RRNA

This provides readback for the last value that was written to FR_NCO_AR.

Note: This value is not synchronized and should only be read while the FR interface is static.

7.5.3.90 TS_TEMP Register (Offset = 0400h) [reset = NA, read-only]

TS_TEMP is shown in Figure 7-137 and described in Table 7-141.

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Temperature Reading in Celsius

Figure 7-137 TS_TEMP Register
76543210
TS_TEMP
R
Table 7-141 TS_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0TS_TEMPRNA

Returns the temperature sensor reading. This returns an unsigned value from 0 to 255. Subtract 80 from this value to get degrees Celsius. For example, a value of 110 indicates 30C.

See Temperature Sensor.

Note: Reads of this register require slower SPI timing. See Switching Characteristics.

Note: This register will not return valid data unless TS_SLEEP=0.

7.5.3.91 TS_SLEEP Register (Offset = 0401h) [reset = 00h]

TS_SLEEP is shown in Figure 7-138 and described in Table 7-142.

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Temperature Sensor Sleep

Figure 7-138 TS_SLEEP Register
76543210
RESERVEDTS_SLEEP
R/W-00hR/W-0b
Table 7-142 TS_SLEEP Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W00h
0TS_SLEEPR/W0bIf temperature conversions are not needed, set this bit to sleep the temperature sensor.

7.5.3.92 SYNC_STATUS Register (Offset = 0410h) [reset = NA]

SYNC_STATUS is shown in Figure 7-139 and described in Table 7-143.

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Synchronization Status

Figure 7-139 SYNC_STATUS Register
76543210
RESERVEDCLK_REALIGNEDCLK_ALIGNEDNCO_SYNC_DETSYSREF_DET
RR/W1CRR/W1CR/W1C
Table 7-143 SYNC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/WNA
3CLK_REALIGNEDR/W1CNAThis bit is set any time the clock dividers associated with SYSREF (excluding LMFC/LEMC) are realigned to SYSREF. This bit is useful to confirm the internally sampled SYSREF signal has a correct and stable period in DDS mode (or for debug purposes in JESD204C mode). Write a 1 to clear this bit.
2CLK_ALIGNEDRNAWhen set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (except for the LMFC/LEMC). Since the LMFC/LEMC does not affect this bit, it is appropriate to use in DDS mode, but can also be used when the JESD204C interface is enabled. This bit is read-only (cannot be cleared via SPI).
1NCO_SYNC_DETR/W1CNAThis bit is set any time one or more NCOs receives a sync event. Write a 1 to clear this bit.
0SYSREF_DETR/W1CNAThis bit is set when a SYSREF is detected. Write a 1 to clear the bit and allow it to be re-detected.

7.5.3.93 SYS_ALM Register (Offset = 0430h) [reset = NA, read/write 1 to clear]

SYS_ALM is shown in Figure 7-140 and described in Table 7-144.

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System Alarm Status

Figure 7-140 SYS_ALM Register
76543210
JESD_LINK_DOWN_ALMJTIMER_EXPIRED_ALMJESD_CRC_ALMRESERVEDSYSRST_ALMSYSREF_ALM
R/W1CR/W1CR/W1CRR/W1CR/W1C
Table 7-144 SYS_ALM Register Field Descriptions
BitFieldTypeResetDescription
7JESD_LINK_DOWN_ALMR/W1CThis bit is set any time LINK_UP transitions from 1 to 0 while JESD_EN=1. Write 1 to clear the alarm.
6JTIMER_EXPIRED_ALMR/W1CThis bit is set if the JESD link has been down (LINK_UP=0 while JESD_EN=1) longer than allowed by JTIMER. Write 1 to clear the alarm.
5JESD_CRC_ALMR/W1CThis bit is set any time CRC_FAULT is detected on an enabled lane. Applies only to 64b/66b modes. Write 1 to clear the alarm.
4-2RESERVEDR
1SYSRST_ALMR/W1CThis bit is set any time the chip is reset due to the RESET ball, power on reset, or SOFT_RESET. Write 1 to clear the alarm.
0SYSREF_ALMR/W1CThis bit is set any time a SYSREF edge is detected at an incorrect alignment by either the clock dividers or by the JESD Subsystem (when JESD_EN=1). Write 1 to clear the alarm.

7.5.3.94 ALM_MASK Register (Offset = 0431h) [reset = 00h]

ALM_MASK is shown in Figure 7-141 and described in Table 7-145.

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Alarm Mask

Figure 7-141 ALM_MASK Register
76543210
JESD_LINK_DOWN_MASKJTIMER_EXPIRED_MASKJESD_CRC_MASKRESERVEDSYSREF_ALM_MASK
R/W-0bR/W-0bR/W-0bR/W-0hR/W-0b
Table 7-145 ALM_MASK Register Field Descriptions
BitFieldTypeResetDescription
7JESD_LINK_DOWN_MASKR/W0hWhen set, alarms from the JESD_LINK_DOWN_ALM register are masked and will not impact the alarm output.
6JTIMER_EXPIRED_MASKR/W0bWhen set, alarms from the JTIMER_EXPIRED_ALM register are masked and will not impact the alarm output.
5JESD_CRC_MASKR/W0bWhen set, alarms from the JESD_CRC_ALM register are masked and will not impact the alarm output.
4-1RESERVEDR/W0h
0SYSREF_ALM_MASKR/W0bWhen set, alarms from the SYSREF_ALM register are masked and will not impact the alarm output.

7.5.3.95 MUTE_MASK Register (Offset = 0432h) [reset = 21h]

MUTE_MASK is shown in Figure 7-142 and described in Table 7-146.

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DAC Mute Mask

Figure 7-142 MUTE_MASK Register
76543210
RESERVEDJESD_CRC_MUTE_MASKRESERVEDSYSREF_MUTE_MASK
R/W-00bR/W-1bR/W-0hR/W-1b
Table 7-146 MUTE_MASK Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00b
5JESD_CRC_MUTE_MASKR/W1bJESD CRC alarms will mute the DACs according to JESD_CRC_REC unless this bit is set.
4-1RESERVEDR/W0h
0SYSREF_MUTE_MASKR/W1bAlarms from the SYSREF_ALM register will mute the DACs unless this bit is set.

7.5.3.96 MUTE_REC Register (Offset = 0433h) [reset = A0h]

MUTE_REC is shown in Figure 7-143 and described in Table 7-147.

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DAC Mute Recovery

Figure 7-143 MUTE_REC Register
76543210
JESD_LINK_DOWN_RECRESERVEDJESD_CRC_RECRESERVED
R/W-1bR/W-0bR/W-1bR/W-00h
Table 7-147 MUTE_REC Register Field Descriptions
BitFieldTypeResetDescription
7-6JESD_LINK_DOWN_RECR/W1b

0: DAC will remain muted until the JESD_LINK_DOWN_ALM = 0.

1: DAC will unmute automatically when the JESD link recovers.

6RESERVEDR/W0b
5JESD_CRC_MUTE_MASKR/W1b

This bit is only used if JESD_CRC_MUTE_MASK = 0.

0: DAC will remain muted until the JESD_CRC_ALM=0

1: DAC will unmute automatically when CRC_FAULT=0.

4-0RESERVEDR/W0h

7.5.3.97 FUSE_STATUS Register (Offset = 0600h) [reset = NA]

FUSE_STATUS is shown in Figure 7-142 and described in Table 7-146.

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Fuse Status

Figure 7-144 FUSE_STATUS Register
76543210
RESERVEDFUSE_DONE
R-NAR-NA
Table 7-148 FUSE_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDRNA
0FUSE_DONERNAReturns ‘1’ when the fuse controller is idle, meaning the controller has completed the fuse auto-load sequence. The sequence takes less than 523,000 CLK cycles to complete, or FUSE_DONE can be polled until it is '1'.

When FUSE_DONE is ‘0’ the user should not read or write any fuse-backed registers.

7.5.3.98 FINE_CUR_A Register (Offset = 0723h) [reset = varies]

FINE_CUR_A is shown in Figure 7-145 and described in Table 7-149.

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Fine Bias Current Control for DACA

Figure 7-145 FINE_CUR_A Register
76543210
RESERVEDFINE_CUR_A
R-00bR/W-varies
Table 7-149 FINE_CUR_A Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00b
5-0FINE_CUR_AR/WvariesFine current control setting for DAC A. See Section 7.3.2.2. The default values varies to match output current specification.

7.5.3.99 COARSE_CUR_A Register (Offset = 0724h) [reset = 0Fh]

COARSE_CUR_A is shown in Figure 7-146 and described in Table 7-150.

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Coarse Bias Current Control for DACA

Figure 7-146 COARSE_CUR_A Register
76543210
DAC0_CBIAS_SLEEPCOARSE_CUR_A
R/W-0hR/W-0xF
Table 7-150 COARSE_CUR_A Register Field Descriptions
BitFieldTypeResetDescription
7-4DAC0_CBIAS_SLEEPR/W0hDAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 8.1.6
3-0COARSE_CUR_AR/W0xFCoarse current control setting for DAC A. See Section 7.3.2.2.

7.5.3.100 FINE_CUR_B Register (Offset = 0725h) [reset = varies]

FINE_CUR_B is shown in Figure 7-147 and described in Table 7-151.

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Fine Bias Current Control for DAC B

Figure 7-147 FINE_CUR_B Register
76543210
RESERVEDFINE_CUR_B
R-00bR/W-varies
Table 7-151 FINE_CUR_B Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00b
5-0FINE_CUR_BR/WvariesFine current control setting for DAC B. See Section 7.3.2.2. The default values varies to match output current specification.

7.5.3.101 COARSE_CUR_B Register (Offset = 0726h) [reset = 0Fh]

COARSE_CUR_B is shown in Figure 7-148 and described in Table 7-152.

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Coarse Bias Current Control for DACB

Figure 7-148 COARSE_CUR_B Register
76543210
DAC1_CBIAS_SLEEPCOARSE_CUR_B
R/W-0hR/W-0xF
Table 7-152 COARSE_CUR_B Register Field Descriptions
BitFieldTypeResetDescription
7-4DAC1_CBIAS_SLEEPR/W0hDAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 8.1.6
3-0COARSE_CUR_BR/W0xFCoarse current control setting for DAC B. See Section 7.3.2.2.

7.5.3.102 DEM_ADJ Register (Offset = 0727h) [reset = 11h]

DEM_ADJ is shown in Figure 7-148 and described in Table 7-152.

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DEM Adjust

Table 7-153 Single Edge DEM Adjust
76543210
DEM_ADJ1DEM_ADJ0
R/W-0x1R/W-0x1
Table 7-154 DEM_ADJ Register Field Descriptions
BitFieldTypeResetDescription
7-4DEM_ADJ1R/W0x1

Adjust DEM behavior for single-edge data-independent DEM for DAC1. This register has no effect unless DAC1 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved.

3-0DEM_ADJ0R/W0x1Adjust DEM behavior for single-edge data-independent DEM for DAC0. This register has no effect unless DAC0 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved.

7.5.3.103 DEM_DITH Register (Offset = 0729h) [reset = 00h]

DEM_DITH is shown in Figure 7-149 and described in Table 7-155.

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DAC DEM and Dither Control

Figure 7-149 DEM_DITH Register
76543210
DEM_DACBDEM_DACADITHER_DACBDITHER_DACA
R/W-00bR/W-00bR/W-00bR/W-00b
Table 7-155 DEM_DITH Register Field Descriptions
BitFieldTypeResetDescription
7-6DEM_DACBR/W00b

0 : Enable single-edge, data-independent DEM for DACB

1 : Enable dual-edge, data-independent DEM for DACB

2 : Enable data-dependent DEM for DACB

3 : DEM disabled for DACB

5-4DEM_DACAR/W00b

0 : Enable single-edge, data-independent DEM for DACA

1 : Enable dual-edge, data-independent DEM for DACA

2 : Enable data-dependent DEM for DACA

3 : DEM disabled for DACA

3-2DITHER_DACBR/W00b

0 : Enable single-edge dithering for DACB

1 : Enable dual-edge dithering for DACB

2 : RESERVED

3 : Dithering disabled for DACB

1-0DITHER_DACAR/W00b

0 : Enable single-edge dithering for DACA

1 : Enable dual-edge dithering for DACA

2 : RESERVED

3 : Dithering disabled for DACA

7.5.3.104 DAC_OFS[0:1] Register (Offset = 072Ah) [reset = 00h]

DAC_OFS[0:1] is described in Table 7-156.

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DAC Offset Control. DAC_OFS[0] is at the lowest address.

Table 7-156 DAC_OFS[0:1] Register Field Descriptions
BitFieldTypeResetDescription
15-13ReservedR/W000b
12-0DAC_OFS[n]R/W00b

Offset adjustment for DACn (n = 0 or 1). The value in this register is added to the DACn output. This is a 2’s complement, 13-bit signed value. The LSB weight is one DAC LSB.

The value programmed into this register passes through a saturation function to limit the adjustment to what is possible. If dithering is enabled on DACn (see DEM_DITH), DAC_OFS[n] is saturated to the range +/- 128. If dithering is disabled on DACn, the saturation range is +/-3968.

See Section 7.3.4.

Note: This value should only be changed when DP_EN=0 or DAC_OFS_CHG_BLK=1.