When phase noise performance is paramount, a discrete analog PLL (APLL) offers substantially lower phase noise than the integrated examples. The trade off is increased SWAP-C. Figure 8-10 shows the block diagram of such an implementation that uses the same Synergy Microwave 8 GHz DRO as the LMX2820 external VCO example discussed previously.

Figure 8-10 Discrete Analog PLL

The APLL outperforms the previous examples by avoiding use of digital dividers and phase detectors, which significantly degrade phase noise. Instead passive diode-based frequency multipliers and mixers are used, which contribute little additive phase noise. Like all synthesizers, a frequency reference with very good close in phase noise, below the loop bandwidth of the APLL, is required for best performance.

In this case, a 1 GHz reference was chosen as the reference is a convenient division of the sample rate and is available either as an output of an R&S SMA100B RF signal generator or as a standalone unit from Wenzel Associates.

As mentioned previously, the APLL does not use digital dividers or phase detectors, which significantly degrade phase noise. Instead the reference is multiplied up to the output frequency using passive multiplier stages (see Figure 8-11). A passive mixer is used as a phase detector that feeds a low noise operational amplifier loop filter. The DRO output is split with one output going to the DAC clock distribution network and the other feeding back into the RF port of the mixer.

Figure 8-11 Reference Multiplier Chain

The multiplier chain uses low noise amplifiers, passive diode multipliers and bandpass filters. For this part of the circuit, what is most critical is the close in phase noise below the loop bandwidth of the PLL. Not all amplifiers demonstrate good close in noise, especially when driven near or into compression. Generally, heterojunction bipolar transistor (HBT) amplifiers, have low flicker noise and operate well when driven into compression.

Bandpass filters were selected to remove the F_IN and 3 x F_IN/2 harmonics that are only partially suppressed by the multipliers. In some implementations the driving amplifier can be filtered to prevent degradation of the harmonic suppression performance. This chain was experimentally optimized, but additional attenuation between stages can be added to manage reflections and amplifier operating conditions.

The loop filter bandwidth is set near where the open loop DRO phase noise crosses the multiplied reference noise with a damping factor set to give a smooth role off that minimizes integrated phase noise. An optional additional feedback cap can be used to speed up the role off if desired (C2 is set roughly to 1/10^th to 1/100^th of C1). The loop filter component values were determined experimentally for this design.

In some implementations a start-up circuit is needed to help the loop acquire lock. In practice we found that the initial power up was all that was needed to get the loop enough of a kick to get the loop to pull in and lock.