JAJSS39A November   2023  – March 2024 DAC39RF10EF , DAC39RFS10EF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
    6. 7.6 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Transmitter Design Procedure
        1. 8.2.3.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.3.1.1 Example 1: SWAP-C Optimized
          2. 8.2.3.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.3.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.3.1.4 10 GHz Clock Generation
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.7.6 Serdes PLL Control

The Serdes recievers work over a wide frequency range if various parameters are altered. Before setting JESD_EN, the user must program various parameters for the Serdes receivers to work. The parameters are adjusted to maintain all these constraints:

  1. The VCO clock frequency (FVCO) must be between 1.5625 GHz and 3.2 GHz.
  2. When the VCO clock frequency (FVCO) is below 2.17 GHz, VRANGE must be set.
  3. The REFDIV, MPY and RATE settings are all associated with a frequency change. The product of all the frequency changes must match the R value for the selected JMODE.
  4. Settings with a higher PLL reference clock (and smaller MPY multiplier) are preferred.
GUID-20211130-SS0I-ST80-1G8M-LGMWQTBLNJF8-low.svgFigure 7-52 Serdes Clock Frequency Generation
Table 7-17 PLL Configuration Table for 8b/10b Encoding Modes
R decimal (fraction) CLK Range (FCLK) (GHz)Register Values to ProgramActual Frequency MultipliersLane Bit Rate (Gbps)
REFDIVMPYRATEVRANGEREFDIVMPYRATE
0.3125 (40/128)2.5-5.120x080x140x3FCLK<3.472GHz1/850.50.78125 – 1.6
0.3125 (40/128)5.0-10.240x100x140x2FCLK<6.994GHz1/16511.5625 – 3.2
0.3125 (40/128)10.0-12.80x200x140x111/32523.125 – 4.0
0.4167 (40/96)1.88-3.840x060x140x3FCLK<2.604GHz1/650.50.78125 – 1.6
0.4167 (40/96)3.75-7.680x0C0x140x2FCLK<5.208GHz1/12511.5625 – 3.2
0.4167 (40/96)7.50-12.80x180x140x1FCLK<10.416GHz1/24523.125 – 5.333
0.625 (40/64)1.25-2.560x040x140x3FCLK<1.736GHz1/450.50.78125 – 1.6
0.625 (40/64)2.5-5.120x080x140x2FCLK<3.472GHz1/8511.5625 – 3.2
0.625 (40/64)5.00-10.240x100x140x1FCLK<6.994GHz1/16523.125 – 6.4
0.625 (40/64)10.00-12.80x200x140x011/32546.25 – 8.0
0.833 (40/48)0.94-1.920x030x140x3FCLK<1.302GHz1/350.50.78125 – 1.6
0.833 (40/48)1.88-3.840x060x140x2FCLK<2.604GHz1/6511.5625 – 3.2
0.833 (40/48)3.75-7.680x0C0x140x1FCLK<5.208GHz1/12523.125 – 6.4
0.833 (40/48)7.50-12.80x180x140x0FCLK<10.416GHz1/24546.25 – 10.667
1 (40/40)0.781-1.60x020x100x3FCLK<1.085GHz1/240.50.78125 – 1.6
1 (40/40)1.5625-3.20x040x100x2FCLK<2.17GHz1/4411.5625 – 3.2
1 (40/40)3.125-6.40x080x100x1FCLK<4.34GHz1/8423.125 – 6.4
1 (40/40)6.25-12.80x100x100x0FCLK<8.68GHz1/16446.25 – 12.8
1.25 (40/32)0.625-1.280x020x140x3FCLK<0.868GHz1/250.50.78125 – 1.6
1.25 (40/32)1.25-2.560x040x140x2FCLK<1.736GHz1/4511.5625 – 3.2
1.25 (40/32)2.5-5.120x080x140x1FCLK<3.472GHz1/8523.125 – 6.4
1.25 (40/32)5.0-10.240x100x140x0FCLK<6.994GHz1/16546.25 – 12.8
1.667 (40/24)0.47-0.960x030x280x3FCLK<0.651GHz1/3100.50.78125 – 1.6
1.667 (40/24)0.94-1.920x030x140x2FCLK<1.302GHz1/3511.5625 – 3.2
1.667 (40/24)1.88-3.840x060x140x1FCLK<2.604GHz1/6523.125 – 6.4
1.667 (40/24)3.75-7.680x0C0x140x0FCLK<5.208GHz1/12546.25 – 12.8
2 (40/20)0.781-1.60x020x100x2FCLK<1.085GHz1/2411.5625 – 3.2
2 (40/20)1.5625-3.20x040x100x1FCLK<2.17GHz1/4423.125 – 6.4
2 (40/20)3.125-6.40x080x100x0FCLK<4.34GHz1/8446.25 – 12.8
2.5 (40/16)0.625-1.280x020x140x2FCLK<0.868GHz1/2511.5625 – 3.2
2.5 (40/16)1.25-2.560x040x140x1FCLK<1.736GHz1/4523.125 – 6.4
2.5 (40/16)2.5-5.120x080x140x0FCLK<3.472GHz1/8546.25 – 12.8
3.3333 (40/12)0.47 – 0.960x030x280x2FCLK<0.651GHz1/31011.5625 – 3.2
3.3333 (40/12)0.94 – 1.920x030x140x1FCLK<1.302GHz1/3523.125 – 6.4
3.3333 (40/12)1.88 – 3.840x060x140x0FCLK<2.604GHz1/6546.25 – 12.8
4 (40/10)0.781 – 1.60x020x100x1FCLK<1.085GHz1/2423.125 – 6.4
4 (40/10)1.5625 – 3.20x040x100x0FCLK<2.17GHz1/4446.25 – 12.8
5 (40/8)0.625-1.280x020x140x1FCLK<0.868GHz1/2523.125 – 6.4
5 (40/8)1.25-2.560x040x140x0FCLK<1.736GHz1/4546.25 – 12.8
Table 7-18 PLL Configuration Table for 64b/66b Encoding Modes
RR decimal (fraction) CLK Range (FCLK) (GHz)Register Values to ProgramActual Frequency MultipliersLane Bit Rate (FBIT) (Gbps)
REFDIVMPYRATEVRANGEREFDIVMPYRATE
0.515625 (33/64)6.06 – 12.410x200x210x1FCLK<8.417GHz1/328.2523.125 – 6.4
0.6875 (33/48)4.55­ – 9.310x180x210x1FCLK<6.313GHz1/248.2523.125 – 6.4
0.6875 (33/48)9.09 – 12.80x300x210x0FCLK<12.625GHz1/488.2546.25 – 8.8
0.825 (33/40)3.79 – 7.760x140x210x1FCLK<5.261GHz1/208.2523.125 – 6.4
0.825 (33/40)7.58 – 12.80x280x210x0FCLK<10.521GHz1/408.2546.25 – 10.56
1.03125 (33/32)3.03 – 6.210x100x210x1FCLK<4.208GHz1/168.2523.125 – 6.4
1.03125 (33/32)6.06 – 12.410x200x210x0FCLK<8.417GHz1/328.2546.25 – 12.8
1.375 (33/24)2.27 – 4.650x0C0x210x1FCLK<3.156GHz1/128.2523.125 – 6.4
1.375 (33/24)4.55 – 9.310x180x210x0FCLK<6.313GHz1/248.2546.25 – 12.8
1.65 (33/20)1.89 – 3.880x0A0x210x1FCLK<2.630GHz1/108.2523.125 – 6.4
1.65 (33/20)3.79 – 7.760x140x210x0FCLK<5.261GHz1/208.2546.25 – 12.8
2.0625 (33/16)1.52 – 3.100x080x210x1FCLK<2.104GHz1/88.2523.125 – 6.4
2.0625 (33/16)3.03 – 6.210x100x210x0FCLK<4.208GHz1/168.2546.25 – 12.8
2.75 (33/12)1.14 – 2.330x060x210x1FCLK<1.578GHz1/68.2523.125 – 6.4
2.75 (33/12)2.27 – 4.650x0C0x210x0FCLK<3.156GHz1/128.2546.25 – 12.8
3.3 (33/10)0.95 – 1.940x050x210x1FCLK<1.315GHz1/58.2523.125 – 6.4
3.3 (33/10)1.89 – 3.880x0A0x210x0FCLK<2.630GHz1/108.2546.25 – 12.8
4.125 (33/8)0.76 – 1.550x040x210x1FCLK<1.052GHz1/48.2523.125 – 6.4
4.125 (33/8)1.52 – 3.100x080x210x0FCLK<2.104GHz1/88.2546.25 – 12.8