JAJSS39A November   2023  – March 2024 DAC39RF10EF , DAC39RFS10EF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
    6. 7.6 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Transmitter Design Procedure
        1. 8.2.3.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.3.1.1 Example 1: SWAP-C Optimized
          2. 8.2.3.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.3.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.3.1.4 10 GHz Clock Generation
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.4 Application Curves

The radar chip waveform used for testing is a non-linear frequency modulated (NLFM) pulse, lasting 4096 samples at the 250 MSPS complex input rate. At baseband the frequency ramps from -100 MHz to + 100MHz, following a frequency ramp curve developed by Price and shown in Equation 6 [Price R. Chebyshev Low Pulse Compression Sidelobes via a Nonlinear FM. National Radio Science Meeting of URSI; PortSaid, Egypt: 1979.] with T = 4096 samples, B = 0.8, Bl = 0.5611 and Bc = 0.238.

Equation 6. ff,Bl, Bc=B×t-T2T×Bl+Bc1-4t-T22T2

The NLFM Chirp frequency ramp is shown in Figure 8-13, complex time domain baseband waveform inFigure 8-14, baseband frequency spectrum in Figure 8-15 and auto-correlation in Figure 8-16.

GUID-20230222-SS0I-CK6D-1M4B-V04038KFFP3X-low.svgFigure 8-13 NLFM Frequency Ramp
GUID-20230222-SS0I-QB3S-LMNN-NSMKCDKFBS5N-low.svgFigure 8-15 Digital Spectrum for NLFM Chirp
GUID-20230222-SS0I-53HG-QK1H-FWBFFRKSLMPT-low.svgFigure 8-14 Complex Time Domain of NLFM Chirp (Red = real, Black = imag)
GUID-20230222-SS0I-QJQC-SNCR-PT4K5ZPM6PTT-low.svgFigure 8-16 Auto-correlation of NLFM Chirp

The output spectra for the NLFM Chirp at 3.2 GHz is shown in Figure 8-17. The largest spur is the duty-cycle image at 4.8 GHz, which is suppressed 50 dB. Figure 8-18 shows a 1 GHz span centered at 3.2 GHz. the interpolation filters confine the output spectrum to a 250 MHz wide band at 3.2 GHz. The spectra purity of the 200 MHz is shown with a fullscale tone in Figure 8-19. The largest spurs are ~ 80 dBc at 3.16 GHz, which is the 4th harmonic (aliased back into 1st Nyquist zone), and the 6th harmonic at ~ 86 dBc.

GUID-20230222-SS0I-2WNS-FFQS-0NTNM41DLPHP-low.svgFigure 8-17 NLFM Chirp Output Spectra across
0 - 8 GHz
GUID-20230222-SS0I-VXVH-HRKG-JZXKQTKM23TQ-low.svgFigure 8-19 In Band Single Tone Frequency Spectra with fOUT = 3.211 GHz
GUID-20230222-SS0I-QGFN-HQH9-FS8C5DMWFDVX-low.svgFigure 8-18 NLFM Chirp Output Spectra across
1 GHz

The output phase noise for a tone at 3.2 GHz using the recommended clocking circuit is shown in Figure 8-20. The additive phase noise for the DAC by itself is shown in Figure 8-21.

Figure 8-20 Output Phase Noise at 3.2 GHz using Recommended Clock Circuit
Figure 8-21 DAC Additive Phase Noise at 3.2 GHz