JAJSS39A November   2023  – March 2024 DAC39RF10EF , DAC39RFS10EF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
    6. 7.6 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Transmitter Design Procedure
        1. 8.2.3.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.3.1.1 Example 1: SWAP-C Optimized
          2. 8.2.3.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.3.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.3.1.4 10 GHz Clock Generation
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics - DC Specifications

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT = 0.64 GSPS, JMODE 4, 8b/10b encoding, 16x Interpolation, FCLK = 10.24 GHz, FOUT = 2997 MHz, NRZ mode, IFSSWITCH = 20.5 mA, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
BITS DAC core resolution 16(1) bits
DNL Differential nonlinearity ±2.2 LSB
INL Integral nonlinearity ±9 LSB
DAC ANALOG OUTPUT (DACOUTA+, DACOUTA–, DACOUTB+, DACOUTB–)
IFS_SWITCH Switched full scale output current 3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B= 0xF and FINE_CUR_A / FINE_CUR_B = default, CUR_2X_EN = 1 41 mA
3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B= 0xF and FINE_CUR_A / FINE_CUR_B = default 20.5
3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0x0 and FINE_CUR_A / FINE_CUR_B = default, CUR_2X_EN  = 1 11
3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0x0 and FINE_CUR_A / FINE_CUR_B = default 5.5
ISTATIC Static output current per pin 3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default 4.8 mA
IFSDRIFT Full scale output current temperature drift 3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default -8.6 uA/℃
-0.3 PPM/℃
IFSERROR Full scale current error 3.6-kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default ±0.1 %
IMIDOFFERR Mid Code Offset Error Mid Code offset ±0.02 %FSR
VCOMP Output compliance voltage range Measured from DACOUTA+, DACOUTA–, DACOUTB+ or DACOUTB– to AGND VDDA18A/B - 0.5 VDDA18A/B + 0.5 V
COUT Output capacitance Single-ended capacitance to ground 0.25 pF
RTERM Output differential termination resistance 102 Ω
RTERMDRIFT Output differential termination resistance temperature coeff –9.6 mΩ/℃
–42 PPM/℃
CLOCK AND SYSREF INPUTS (CLK+, CLK-, SYSREF+, SYSREF-)
RT Internal differential termination resistance 100 Ω
CIN Internal differential input capacitance 0.5 pF
REFERENCE VOLTAGE
VREF Reference output voltage 0.9 V
VREF-DRIFT Absolute Value of Reference output voltage drift over temperature 45 ppm/°C
IREF Maximum reference output current sourcing capability for EXTREF ball with internal reference 100 nA
JESD204C SERDES INTERFACE ([15:0]SRX+/-)
VSRDIFF SerDes Receiver Input Amplitude 50 1200 mVppdiff
VSRCOM SerDes Input Common Mode Internal AC coupled
ZSRdiff SerDes Internal Differential Termination 100 Ω
CMOS INTERFACE (ALARM, SCLK, SCS, SDI, SDO, RESET, FRDI[0:3], FRCLK, FRCS, SYNC, TXENABLE[0:1])
IIH High level input current (with pulldowns) SCANEN(2) 200 uA
IIH High level input current (without pulldowns) SCS, RESET, FRCS, TXEN[0:1],  FRDI[0:3], FRCLK, SDI,  SCLK(2) 2 uA
IIL Low level input current (with pullups) SCS, RESET, FRCS, TXEN[0:1](2) –200 uA
IIL Low level input current (without pullups) SCANEN, FRDI[0:3], FRCLK, SDI,  SCLK(2) –3 uA
CI Input capacitance Input capacitance 3 pF
VIH High level input voltage SCLK, SCS, SDI, RESET, FRDI[0:3], FRCLK, FRCS, SCANEN, TXEN[0:1] 0.7 x
VDDIO18		 V
VIL Low level input voltage 0.3 x
VDDIO18		 V
VOH High level output voltage ALARM, SDO, SYNC, ILOAD = –400 uA 1.55 V
VOL Low level output voltage ALARM, SDO, SYNC, ILOAD = 400 uA 0.2 V
TEMPERATURE SENSOR
Res Resolution 1 ℃/LSB
Range Digital Range -50 150 ℃
TERROR Temperature Error TA = 25℃, device powered down except for temperature sensor and SPI interface ±5 ℃
(1) Input resolution is limited based on the values in Resolution Limitation at Output of JESD204C Block
(2) With no IO supply voltage offset in connecting device.