JAJSS39A November   2023  – March 2024 DAC39RF10EF , DAC39RFS10EF

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
    6. 7.6 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Transmitter Design Procedure
        1. 8.2.3.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.3.1.1 Example 1: SWAP-C Optimized
          2. 8.2.3.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.3.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.3.1.4 10 GHz Clock Generation
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics - Power Consumption

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT =640 MSPS, JMODE 4, 64b/66b encoding, 16x Interpolation, FCLK = 10.24 GHz, FOUT = 2997 MHz, NRZ mode, IFSSWITCH = 20.5 mA, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 1: Dual DACs, 1 IQ input stream per DAC, FINPUT = 640 MSPS, JMODE 4, 16x Interpolation, FDAC = 10.24 GSPS, FOUT = 2997 MHz, NRZ mode (dual channel version only) 85 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 103
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 325
IVDDCLK 1.0-V supply current for VDDCLK10 496
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2120
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123
PDIS Total power dissipation 3500 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 2: Dual DACs, 2 IQ input streams per DAC, FINPUT = 640 MSPS, JMODE 3, 16x Interpolation, FDAC = 10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 399 7MHz, NRZ mode (dual channel version only) 85 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 153
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 328
IVDDCLK 1.0-V supply current for VDDCLK10 497
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 3270
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 122
PDIS Total power dissipation 4740 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 3: Dual DACs, 2 IQ input streams per DAC, FINPUT = 160 MSPS, JMODE 6, 64x Interpolation, FDAC = 10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) 85 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 102
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327
IVDDCLK 1.0-V supply current for VDDCLK10 496
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2150
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123
PDIS Total power dissipation 3540 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 4: Dual DACs, 2 IQ input streams per DAC, FINPUT = 160 MSPS, JMODE 5, 64x Interpolation, FDAC =10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) 85 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 103
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327
IVDDCLK 1.0-V supply current for VDDCLK10 496
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2240
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123
PDIS Total power dissipation 3620 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 5: Dual channel devices programmed as single DAC, FINPUT = 20.48 GSPS, JMODE 14 (8-bit resolution), FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode 58 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 153
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 311
IVDDCLK 1.0-V supply current for VDDCLK10 497
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2040
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70
PDIS Total power dissipation 3350 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 6: Single channel devices (DAC39RFSxx), 1 IQ input stream, FINPUT = 640 GSPS, JMODE 4, 16x Interpolation, FDAC = 10.24 GSPS, FOUT = 2997 MHz, NRZ mode 58 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 102
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 163
IVDDCLK 1.0-V supply current for VDDCLK10 308
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1270
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70
PDIS Total power dissipation 2160 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 7: Single channel devices (DAC39RFSxx), 2 IQ input streams, FINPUT = 160MSPS, JMODE 6, 64x Interpolation, FDAC = 10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode 58 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 102
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 163
IVDDCLK 1.0-V supply current for VDDCLK10 308
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1310
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70
PDIS Total power dissipation 2200 mW
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 8: Single channel devices (DAC39RFSxx), FINPUT = 20.48GSPS, JMODE 14 (8-bit resolution), FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode 58 mA
IVDDIO 1.8-V supply current for VDDIO 1
IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 154
IVDDL 1.0-V combined supply current for VDDLB, VDDLA 162
IVDDCLK 1.0-V supply current for VDDCLK10 309
IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1710
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70
PDIS Total power dissipation 2690 mW
PDIS Total power dissipation Power Mode 14: Sleep, MODE[1:0] = 0b11. 171 mW