JAJSLP4A
December 2021 – May 2024
DAC43508
,
DAC53508
,
DAC63508
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configurations and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements: SPI
5.7
Timing Requirements: Logic
5.8
Timing Diagrams
5.9
Typical Characteristics: Static Performance
5.10
Typical Characteristics: Dynamic Performance
5.11
Typical Characteristics: General
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Digital-to-Analog Converter (DAC) Architecture
6.3.1.1
DAC Transfer Function
6.3.1.2
DAC Register Update and LDAC Functionality
6.3.1.3
CLR Functionality
6.3.1.4
Output Amplifier
6.3.2
Reference
6.3.3
Power-On Reset (POR)
6.3.4
Software Reset
6.4
Device Functional Modes
6.4.1
Power-Down Mode
6.5
Programming
6.5.1
Serial Peripheral Interface (SPI)
7
Register Map
7.1
DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
7.2
STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
7.3
BRDCAST Register (address = 03h) [reset = 0000h]
7.4
DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Programmable LED Biasing
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
8.2.2
Programmable Window Comparator
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTE|16
MPQF149D
サーマルパッド・メカニカル・データ
RTE|16
QFND525B
発注情報
jajslp4a_oa
jajslp4a_pm
8.2
Typical Applications