JAJSLP1 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics: Comparator Mode
   6. 6.6  Electrical Characteristics: General
   7. 6.7  Timing Requirements: I2C Standard Mode
   8. 6.8  Timing Requirements: I2C Fast Mode
   9. 6.9  Timing Requirements: I2C Fast-Mode Plus
   10. 6.10 Timing Requirements: SPI Write Operation
   11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
   12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
   13. 6.13 Timing Requirements: PWM Output
   14. 6.14 Timing Diagrams
   15. 6.15 Typical Characteristics
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
         1. 7.3.2.1 Voltage Reference and DAC Transfer Function
         2. 7.3.2.2 Power-Supply as Reference
         3. 7.3.2.3 Internal Reference
         4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
         1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
            1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
            2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
   4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
   5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
         1. 7.5.2.1 F/S Mode Protocol
         2. 7.5.2.2 I2C Update Sequence
            1. 7.5.2.2.1 Address Byte
            2. 7.5.2.2.2 Command Byte
         3. 7.5.2.3 I2C Read Sequence
   6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
         1. 8.2.1.1 Design Requirements
         2. 8.2.1.2 Detailed Design Procedure
         3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
         1. 8.2.2.1 Design Requirements
         2. 8.2.2.2 Detailed Design Procedure
   3. 8.3 Power Supply Recommendations
   4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
11. 10Mechanical, Packaging, and Orderable Information

DAC4390x-Q1 車載用スマート DAC、対数フェードイン・フェードアウトおよびシーケンシャル・ターン・アニメーション用、I²C、SPI、GPIO、PWM インターフェイス搭載

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。