JAJSLP1 September   2023 DAC43901-Q1 , DAC43902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Comparator Mode
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast-Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
        2. 7.3.2.2 Power-Supply as Reference
        3. 7.3.2.3 Internal Reference
        4. 7.3.2.4 External Reference
      3. 7.3.3 Programming Interface
      4. 7.3.4 Nonvolatile Memory (NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.4.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.4.1.2 NVM-CRC-FAIL-INT Bit
      5. 7.3.5 Power-On Reset (POR)
      6. 7.3.6 External Reset
      7. 7.3.7 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
      2. 7.4.2 PWM Fade-In Fade-Out Mode
      3. 7.4.3 Sequential Turn-Indicator Animation Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Sequential Turn Indicator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Logarithmic Fade-In Fade-Out
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230927-SS0I-MQHP-RQZ8-RH7BQJRMVFKM-low.svg Figure 5-1 DAC43901-Q1: RTE Package, 16-pin WQFN (Top View)
GUID-20230927-SS0I-FR6N-9NF9-VJ25B15HWFCJ-low.svg Figure 5-2 DAC43902-Q1: RTE Package, 16-pin WQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
DAC43901-Q1 DAC43902-Q1
1 TRIG-IN TRIG-IN Input Trigger input. This pin acts as the trigger input for fade-in fade-out or animation application.
2-4 NC NC — No connection. Solder this pin to the pad.
5 SDO/NC SDO/PWM3 Output SDO: Serial data output for SPI in programming mode (VREF/MODE pin is low). When configured as SDO, connect this pin to the I/O voltage with an external pullup resistor.NC: No connection in standalone mode. Solder this pin to the pad.PWM3: PWM output channel 3 in standalone mode (VREF/MODE pin is high). This pin must be connected to the I/O voltage using an external pullup resistor.
6 SCL/SYNC/NC SCL/SYNC/PWM2 Output SCL: I2C serial interface clock or SPI chip select input in programming mode (VREF/MODE pin is low). This pin must be connected to the I/O voltage using an external pullup resistor.SYNC: Synchronize pin in programming mode. NC: No connection in standalone mode. Solder this pin to the pad.PWM2: PWM output channel 2 in standalone mode (VREF/MODE pin is high). This pin must be connected to the I/O voltage using an external pullup resistor.
7 A0/SDI/PWM1 A0/SDI/PWM1 Input A0: Address configuration input for I2C or serial data input for SPI in programming mode (VREF/MODE pin is low). When set to A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration. SDI: Serial data input for SPI in programming mode. When used as SDI, do not pull up or pull down this pin. PWM1: PWM output channel 1 in standalone mode (VREF/MODE pin is high). Connect this pin to the I/O voltage using an external pullup resistor.
8 SDA/SCLK/PWM0 SDA/SCLK/PWM0 Input/Output SDA: Bidirectional I2C serial data bus in programming mode (VREF/MODE pin is low).SCLK: SPI clock input in programming mode.PWM0: PWM output channel 0 in standalone mode (VREF/MODE pin is high). Connect this pin to the I/O voltage using an external pullup resistor.
9-10 NC NC — No connection. Solder this pin to the pad.
11 NC TRIG-OUT Output NC: No connection. Solder this pin to the pad. TRIG-OUT: Trigger output. Connect this pin to pin 12.
12 NC TRIG-OUT Input/Output NC: No connection. Solder this pin to the pad. TRIG-OUT: Trigger output. Connect this pin to pin 11.
13 CAP CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
14 AGND AGND Ground Ground reference point for all circuitry on the device.
15 VDD VDD Power Supply voltage: 1.8 V to 5.5 V.
16 VREF/MODE VREF/MODE Input External reference or interface mode select input.
Connect a capacitor (approximately 0.1 μF) between VREF/MODE and AGND. Use a pullup resistor to VDD when the external reference is not used. In case an external reference is used or when in interface select mode, make sure the reference ramps up after VDD. In interface select mode:
Pull this pin low to enable I2C or SPI communication.
Pull this pin high to enable standalone mode.
Thermal Pad Thermal Pad Thermal Pad Ground Connect the thermal pad to AGND.