The DAC43901-Q1 support a state-machine preconfigured for PWM (pulse-width-modulation) fade-in fade-out, used for smooth dimming of lights and starting of motors. The fade-in fade-out is done logarithmically. DAC channel 0 is used as a comparator and the TRIG-IN pin is used as the trigger input for the fade-in fade-out. The PWM outputs are available on the digital pins in standalone mode. The device goes into the standalone mode when the VREF/MODE pin is pulled high. In this mode, the programming interface is disabled. The digital programming interface (I²C and SPI) pins are open-drain outputs and must be pulled up to function as PWMx outputs. In standalone mode, the device runs using the configurations in NVM. Pulling the VREF/MODE pin low brings the device into programming mode. When the PWM output mode is enabled, all four programming interface pins act as PWMx outputs, even if not used. Partial selection is not possible. The fade-in fade-out PWM output is available on PWM0 (SDA/SCLK) and PWM1 (A0/SDI). Table 7-9 shows the PWM output mapping on the digital pins. The PWM duty-cycle resolution is 7 bits. The PWM0 transitions from the predefined minimum duty cycle to the maximum duty cycle on the rising edge of the trigger input and transitions from the maximum duty cycle to minimum duty cycle on the falling edge of the trigger input. The fade-in fade-out configurations for PWM0 are programmed using the SRAM or the register addresses shown in Table 7-10.

Figure 7-4 PWM Fade-In Fade-Out

Figure 7-5 Fade-In Fade-out High-Level Timing Diagram

By default the DAC43901-Q1 is configured in the PWM fade-in fade-out with the default settings as shown in Table 7-10. To change settings in the SRAM, write the SRAM address to the SRAM-ADDR register followed by a write to the SRAM-DATA register with the data. The register locations can be directly written with a single I²C or SPI sequence. In fade-in fade-out mode or animation mode, the basic setting is the fade-in or fade-out SLEW_RATE as depicted in Figure 7-6. The SLEW_RATE defines the timing resolution of the application. When the SLEW_RATE is multiplied with the number of steps in the fading, the fading time is obtained. The SLEW_RATE can be calculated using Equation 4. In logarithmic fading, the number of steps are nonlinear and also depend on the start and end duty-cycle settings. The total fading time is calculated using Equation 5 and Table 7-5. The fade-in can be started after a delay, calculated per Equation 7. CH0-DELAY defines the fade-in delay for PWM0, and COM-DELAY defines the fade-in delay for PWM1. The delay applies even when the fade-in is disabled by writing 0 for FADE-IN SLEW_RATE. In this case, a predefined delay setting of 256 is considered. There is no delay for fade-out.

Figure 7-6 Fade-in Fade-Out Detailed Timing Diagram

where:

• t_{SLEW_RATE} is the fade-in or fade-out unit time in microseconds/step.
• SLEW_RATE is the FADE-IN SLEW-RATE or FADE-OUT SLEW-RATE as specified in Table 7-10.

The pseudocode to compute the fade-in and fade-out steps is as follows:

min_duty = <user input>
max_duty = <use input>
if(min_duty == 0)
  min_duty = 1
#IF FADE-IN
current_duty = min_duty << 5
next_duty = integer(current_duty + (current_duty >> 5))
#ELIF FADE-OUT
current_duty = max_duty << 5
next_duty = integer(current_duty - (current_duty >> 5))
#ENDIF
current_duty = next_duty
output_duty = integer(next_duty >> 5)
#IF FADE-IN
if(output_duty > max_duty)
  output = max_duty
else
  output = output_duty
#ELIF FADE-OUT
if(output_duty < min_duty)
  output = min_duty
else
  output = output_duty
#ENDIF

where:

• t_FADE is the total fading (fade-in or fade-out) time as depicted in Figure 7-6.
• t_{SLEW_RATE} is the fade-in or fade-out time slice in seconds/step.
• SLEW_RATE is the FADE-IN SLRE-RATE or FADE-OUT SLEW-RATE, as specified in Table 7-10.
• n is the CODE corresponding to the PWM duty cycle, as specified in Table 7-5.
• PWM_START is the PWM-MIN value for fade-in and PWM-MAX value for fade-out, as specified in Table 7-10.
• PWM_END is the PWM-MAX value for fade-in and PWM-MIN value for fade-out, as specified in Table 7-10.
• REPETATION(n) is the REPETITION(CODE) value specified for every PWM code, as specified in Table 7-5.

Table 7-11 shows the list of register settings done for the device configuration.

The duty cycle of the PWM is proportional to the 7-bit code, 0d to 126d. As Table 7-8 shows, the code 127d corresponds to 100% duty cycle. The duty cycle 99.22% (127d/128d) is skipped to achieve 100% duty cycle using a 7-bit code. The PWM duty-cycle setting is done by the state machine and is not exposed to the user.