JAJSON3 May   2022 DAC53001 , DAC53002 , DAC63001 , DAC63002

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
        1. 7.4.7.1 Deep-Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 特長

  • 柔軟な構成でプログラム可能な電圧または電流出力：
    • 電圧出力：
      • 1 LSB INL および DNL (10 ビット)
      • 1x、1.5x、2x、3x、4x のゲイン
    • 電流出力：
      • 1 LSB INL および DNL (8 ビット)
      • 25μA～250μA のユニポーラおよびバイポーラ出力範囲オプション
  • 電圧出力モードで 35μA/チャネルの IDD
  • すべてのチャネルでコンパレータ・モードをプログラム可能
  • VDD オフ時はハイ・インピーダンス出力
  • ハイ・インピーダンスおよび抵抗性プルダウンのパワー・ダウン・モード
  • 50MHz、SPI 互換インターフェイス
  • I2C、PMBus™、SPI インターフェイスを自動検出
    • VIH：1.62V (VDD = 5.5V の場合)
  • 汎用入出力 (GPIO) をさまざまな機能に構成可能
  • あらかじめ定義された波形生成：正弦波、余弦波、三角波、のこぎり波
  • ユーザーがプログラム可能な不揮発性メモリ (NVM)
  • 基準電圧として、内部、外部または電源を使用可能
  • 幅広い動作範囲：
    • 電源：1.8V～5.5V
    • 温度：-40℃～+125℃
  • 超小型パッケージ：16 ピン WQFN (3mm × 3mm)