JAJSON3 May   2022 DAC53001 , DAC53002 , DAC63001 , DAC63002

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
        1. 7.4.7.1 Deep-Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Register Map

Table 7-20 Register Map
REGISTER(1)(2) MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NOP NOP
DAC-X-MARGIN-HIGH DAC-X-MARGIN-HIGH X
DAC-X-MARGIN-LOW DAC-X-MARGIN-LOW X
DAC-X-VOUT-CMP-CONFIG X VOUT-X-GAIN X CMP-X-OD-EN CMP-X-OUT-EN CMP-X-HIZ-IN-DIS CMP-X-INV-EN CMP-X-EN
DAC-X-IOUT-MISC-CONFIG X IOUT-X-RANGE X
DAC-X-CMP-MODE-CONFIG X CMP-X-MODE X
DAC-X-FUNC-CONFIG CLR-SEL-X SYNC-CONFIG-X BRD-CONFIG-X FUNC-GEN-CONFIG-BLOCK-X
DAC-X-DATA DAC-X-DATA X
COMMON-CONFIG WIN-LATCH-EN DEV-LOCK EE-READ-ADDR EN-INT-REF VOUT-PDN-0 IOUT-PDN-0 X VOUT-PDN-1 IOUT-PDN-1
COMMON-TRIGGER DEV-UNLOCK RESET LDAC CLR X FAULT-DUMP PROTECT READ-ONE-TRIG NVM-PROG NVM-RELOAD
COMMON-DAC-TRIG RST-CMP-FLAG-1 TRIG-MAR-LO-1 TRIG-MAR-HI-1 START-FUNC-1 X RST-CMP-FLAG-0 TRIG-MAR-LO-0 TRIG-MAR-HI-0 START-FUNC-0
GENERAL-STATUS NVM-CRC-FAIL-INT NVM-CRC-FAIL-USER X DAC-BUSY-0 X DAC-BUSY-1 NVM-BUSY DEVICE-ID
CMP-STATUS X PROTECT-FLAG WIN-CMP-0 X WIN-CMP-1 CMP-FLAG-0 X CMP-FLAG-1
GPIO-CONFIG GF-EN DEEP-SLEEP-EN GPO-EN GPO-CONFIG GPI-CH-SEL GPI-CONFIG GPI-EN
DEVICE-MODE-CONFIG RESERVED DIS-MODE-IN RESERVED PROTECT-CONFIG RESERVED X
INTERFACE-CONFIG X TIMEOUT-EN X EN-PMBUS X FAST-SDO-EN X SDO-EN
SRAM-CONFIG X SRAM-ADDR
SRAM-DATA SRAM-DATA
BRDCAST-DATA BRDCAST-DATA X
PMBUS-PAGE PMBUS-PAGE Not applicable
PMBUS-OP-CMD PMBUS-OPERATION-CMD-X Not applicable
PMBUS-CML X CML X Not applicable
PMBUS-VERSION PMBUS-VERSON Not applicable
(1) The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
(2) X = Don't care.
Table 7-21 Register Names
I2C/SPI ADDRESS PMBUS PAGE ADDR PMBUS REGISTER ADDR REGISTER NAME SECTION
00h FFh D0h NOP Section 7.6.1
01h 00h 25h DAC-1-MARGIN-HIGH Section 7.6.2
02h 00h 26h DAC-1-MARGIN-LOW Section 7.6.3
03h FFh D1h DAC-1-VOUT-CMP-CONFIG Section 7.6.4
04h FFh D2h DAC-1-IOUT-MISC-CONFIG Section 7.6.5
05h FFh D3h DAC-1-CMP-MODE-CONFIG Section 7.6.6
06h FFh D4h DAC-1-FUNC-CONFIG Section 7.6.7
13h 03h 25h DAC-0-MARGIN-HIGH Section 7.6.1
14h 03h 26h DAC-0-MARGIN-LOW Section 7.6.2
15h FFh DDh DAC-0-VOUT-CMP-CONFIG Section 7.6.3
16h FFh DEh DAC-0-IOUT-MISC-CONFIG Section 7.6.4
17h FFh DFh DAC-0-CMP-MODE-CONFIG Section 7.6.5
18h FFh E0h DAC-0-FUNC-CONFIG Section 7.6.6
19h 00h 21h DAC-1-DATA Section 7.6.8
1Ch 03h 21h DAC-0-DATA Section 7.6.8
1Fh FFh E3h COMMON-CONFIG Section 7.6.9
20h FFh E4h COMMON-TRIGGER Section 7.6.10
21h FFh E5h COMMON-DAC-TRIG Section 7.6.11
22h FFh E6h GENERAL-STATUS Section 7.6.12
23h FFh E7h CMP-STATUS Section 7.6.13
24h FFh E8h GPIO-CONFIG Section 7.6.14
25h FFh E9h DEVICE-MODE-CONFIG Section 7.6.15
26h FFh EAh INTERFACE-CONFIG Section 7.6.16
2Bh FFh EFh SRAM-CONFIG Section 7.6.17
2Ch FFh F0h SRAM-DATA Section 7.6.18
50h FFh F1h BRDCAST-DATA Section 7.6.19
NA All pages 00h PMBUS-PAGE Section 7.6.20
NA 00h 01h PMBIS-OP-CMD-0 Section 7.6.21
NA 01h 01h PMBUS-OP-CMD-1 Section 7.6.21
NA 02h 01h PMBUS-OP-CMD-2 Section 7.6.21
NA 03h 01h PMBUS-OP-CMD-3 Section 7.6.21
NA All pages 78h PMBUS-CML Section 7.6.22
NA All pages 98h PMBUS-VERSION Section 7.6.23
Table 7-22 Access Type Codes
Access TypeCodeDescription
XXDon't care
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value