JAJSQ25 march 2023 DAC53004W
PRODUCTION DATA
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
A1 | VREF | Power | External
reference input. Connect a capacitor (approximately 0.1 μF) between
VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. Do not ramp up this pin before VDD. In case an external reference is used, make sure the reference ramps up after VDD. |
A2 | OUT3 | Output | Analog output voltage from DAC channel 3. |
A3 | OUT2 | Output | Analog output voltage from DAC channel 2. |
A4 | GPIO/SDO | Input/Output | General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS. For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD. |
B1 | VDD | Power | Supply voltage. |
B2 | FB3 | Input | Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current. |
B3 | FB2 | Input | Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current. |
B4 | SCL/SYNC | Output | I2C serial interface clock or SPI chip select input. Connect this to the IO voltage using an external pullup resistor. This pin can ramp up before VDD. |
C1 | AGND | Ground | Ground reference point for all circuitry on the device. |
C2 | FB0 | Input | Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current. |
C3 | FB1 | Input | Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current. |
C4 | A0/SDI | Input | Address
configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1). For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD. |
D1 | CAP | Power | External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND. |
D2 | OUT0 | Output | Analog output voltage from DAC channel 0. |
D3 | OUT1 | Output | Analog output voltage from DAC channel 1. |
D4 | SDA/SCLK | Input/Output | Bidirectional I2C serial data bus or SPI clock input. Connect this pinto the IO voltage using an external pullup resistor in I2C mode. This pin can ramp up before VDD. |